- 78MSPS operation
- Low power, 145mW/channel, 52MHz, December = 192
- Two independent channels with 14-bit input
- Serial daisy-chain mode for four receivers
- Image rejection greater than 100dB
- >100dB non-parasitic dynamic range
- 0.02Hz adjustment analysis
- User-programmable AGC with enhanced power detector
- The channel filter consists of a 21-tap, 63-tap symmetrical flight information region followed by a fourth-order CIC
- The FIR filter processes 21 bits of data with 16-bit programmable coefficients
- Two independent FIR coefficients can be routed to the memory of one or two channels.
- Flexible output formats include 12-bit floating point or 8, 16, 24, and 32-bit fixed point
- Serial and parallel output ports
- JTAG boundary scan
- 8-bit microprocessor interface
- 128-pin PQFP and 128-pin FBGA packages
- 100% software compatible with CLC5902
- In addition to the VDD voltage pin-compatible CLC5902
illustrate
The CLC5903 dual digital tuner/AGC IC is a dual digital downconverter (DDC) with integrated automatic gain control (AGC). The CLC5903 is a key component in Enhanced Diversity Receiver Chips (EDRCS), which includes the CLC5903 dual digital tuner/automatic gain control, two CLC5957 12-bit analog-to-digital converters (ADCs), and two CLC5526 digitally controlled variable gain amplifiers (DVGAs). The system directly samples the IF signal to enhance receiver performance and reduce system cost by 300MHz.
The CLC5903 is a replacement for the enhanced receiver chipset (NDRC) CLC5902. The main improvements over the CLC5902 are a 50% increase in maximum sample rates of 52MHz to 78MHz, a 62% reduction in power consumption from 760mW to 290mW, and increased flexibility for independent programs in both channel filter factors.
The CLC5903 provides high dynamic range digital tuning and filtering hardwired digital signal processing (DSP) technology based on it. Each channel has independent tuning, phase offset, filter coefficients, and gain settings. Channel filtering consists of a series of three filters. The first is a 4-cascade integral comb (CIC) filter with a programmable decimation ratio from 8 to 2048. This is followed by two symmetrical FIR filters, a 21-tap and a 63-tap, with two independent programmable coefficients. The first FIR filter extracts data from 2, determined by a 2 or 4 second flight information region. The channel filter bandwidth of 52MSPS ranges from ± 650kHz down ± 1.3kHz. At 78MSPS, the maximum bandwidth is increased to ± 975kHz.
The AGC controller of the CLC5903 monitors the output of the ADC and controls the input signal level of the ADC by adjusting the settings of the DVGA. AGC threshold, dead zone + hysteresis, cycle time constant are user defined. The total dynamic range is greater than 120 dB full-scale signal noise at 200kHz bandwidth can be achieved with diversity with the receiver chip.
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- Cellular base stations
- Satellite receiver
- Wireless local loop receiver
- Digital communications
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