- 78MSPS operation
- Low power consumption, 145mW/channel, 52MHz, December = 192
- Two independent channels of 14-bit input
- 4. Serial daisy chain mode of the receiver
- Image rejection of well over 100dB
- Greater than 100dB without parasitic dynamic range
- 0.02Hz adjustment parsing
- User-programmable AGC with enhanced power detector
- The channel filter includes a 21-tap, 63-tap symmetrical FIR fourth-order CIC secondary
- With 16-bit programmable coefficient FIR filter process 21-bit data
- Two independent FIR coefficients can be routed to the memory of one or both channels.
- Flexible output formats include 12-bit floating-point or 8, 16, 24, and 32-bit fixed-point
- Serial and parallel output ports
- JTAG boundary scan
- 8-bit microprocessor interface
- 128-pin PQFP and 128-pin FBGA packages
- 100% software-compatible CLC5902
- In addition to VDD voltage pin compatible CLC5902
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illustrate
CLC5903 dual digital tuner/AGC IC is a dual-channel digital downconverter (DDC) with integrated automatic gain control (AGC). CLC5903 is a key component of the Enhanced Diversity Receiving Chip (EDRCS), which includes CLC5903 dual digital tuners/automatic gain control, two CLC5957 12-bit analog-to-digital converters (ADCs), and two CLC5526 digitally controlled variable gain amplifiers (DVGAs). The system can directly sample the signal in the mid-frequency, enhancing the performance of the receiver and reducing the system cost by 300MHz.
CLC5903 is to strengthen the replacement of the receiver chipset (NDRC) CLC5902. The main improvements in the relative CLC5902 are a 50% increase, a 62% reduction in power consumption from 760mW to 290mW at a maximum sampling rate of 52MHz to 78MHz, and an increase in the flexibility of independent programs on both channels of filter coefficients.
CLC5903 based on digital signal processing (DSP) technology that provides digital tuning and filtered hardwired with high dynamic range. Each channel has independent tuning, phase offset, filter factor, and gain settings. Channel filtering consists of a series of triple filters. The first is a 4-step cascade integral comb (CIC) with a programmable extraction ratio from 8 to 2048 filters. This is followed by two symmetrical FIR filters, 21 taps and a 63 tap, two independent programmable factors. The first FIR filter extracts data from 2 and is determined by a 2 or 4 second FIR. The channel filter bandwidth ranges from ± 650 kHz to ± 1.3 kHz. At 78MSPS, the maximum bandwidth is increased to ± 975kHz.
The CLC5903 AGC controller monitors the output of the ADC and controls the input signal level of the ADC by adjusting the settings of the DVGA. AGC threshold, dead zone + hysteresis, and cycle time constants are user-defined. The total dynamic range is greater than 120 dB and the full scale signal noise is 200kHz, and the bandwidth can reach with a variety of receiving chips.
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- Cellular base stations
- Satellite receiver
- Wireless local loop receiver
- Digital communication
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