- The PCI MAC/strand BIU compliant with IEEE 802.3, version 2.2 supports data transfer rates of 10 Mb/s Ethernet and traditional 100 Mb/s fast Ethernet (via internal physics).
- Bus host - burst size up to 128 segments aligned (512 bytes)
- 97 BIU complies with the Computer and PC 98 Hardware Design Guide, Computer 99 Hardware Design Guidelines draft, supports ACPI 1.0, PCI Power Management Specification 1.1, OnNow Device Power Management Reference Specification - Network Device Version 1.0a
- Wake on the Local Area Network (WOL) supports PC98 standards, PC99, SecureOn, and OnNow, including directional packets, magic packets, VLAN packets, ARP packets, pattern-matched packets, and Phy position change
- Clkrun's PCI Design Guide for Mobile Features
- Virtual Local Area Network (VLAN) and long frame support
- Supports IEEE 802.3x full-duplex flow control
- Extremely flexible Rx packet filtering, including: improved highest bit mask with single address, broadcast, multicast entries 512/unicast hash table, deep packet filtering modes with up to 4 unique pattern matching
- Statistics aggregate RFC 1213 (MIB II) and RFC 1398 (ether-like MIB), compliant with IEEE 802.3 London Metal Exchange support, reducing CPU overhead management
- Internally, 2 KB of data is sent and received by FIFO 2 KB
- Equipped with automatic configuration ports, serial EEPROM loads data from EEPROM
- The flash/PROM interface supports remote startup
- Fully integrated IEEE 802.3/802.3u 3.3 physical layer CMOS
- The IEEE 802.3 compliant 10BASE-T transceiver features integrated filters
- A transceiver compliant with IEEE 802.3u 100BASE-TX
- Fully integrated adaptive balancing and baseline drift compensation in the ANSI X3.263 standard TP-PMD physical sublayer
- Compliant with IEEE 802.3u automatic negotiation – advertising function configured via EEPROM
- Full-duplex supports data transfer rates of 10 and 100 Mb/s
- A single 25 MHz reference clock
- 144-pin LQFP and 160-pin LBGA packages
- The low-power 3.3V CMOS design and operation consisted of 561 milliwatts, 380 milliwatts in wake-up mode, and 33 mW in typical sleep mode
- MII compliant with IEEE 802.3u connectivity replaces external physical layer devices
illustrate
DP83816 is a single-chip PCI bus Ethernet controller with a 10/100 Mb/s bandwidth. This is aimed at low-cost, high-capacity PC motherboards, adapter cards, and embedded systems. This DP83816 fully implements version 2.2 33 power management and supports host communication via MHz PCI bus interface. Packet descriptors and data transmission are controlled via bus, reducing the load on the host CPU. This DP83816 can support full-duplex 10/100 Mb/s transmission and receive with minimal frame gaps.
This DP83816 device is an enhanced version of the National Semiconductor PCI MAC/Plant BIU (Media Access Controller/Bus Interface Unit) integrated with a 3.3V CMOS physical layer interface.
|