- DC - 3.125 Gbps low jitter, high immunity to interference, low power operation
- Reception equalization reduces ISI jitter due to media loss
- Send pre-weighted lossy backplane drivers and cables
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On-chip 100Ω input and output terminations minimize insertion and return losses, reduce component count, and reduce board space. DS25BR101 eliminates on-chip input terminations and increases design flexibility.
- ESD protection on the 7 kV LVDS I/O pin adjacent components
- Small 3 mm x 3 mm LLP-8 space-saving package
illustrate
DS25BR100 chip and DS25BR101 are single-channel 3.125 Gbps LVDS buffers, high-speed signal transmission, optimized lossy FR-4 printed circuit board backplane and balanced metal cables. Fully differential signal paths ensure excellent signal integrity and noise immunity.
DS25BR100 chip transmits pre-emphasis (PE) and receive equalization (EQ) with DS25BR101 functions, making them ideal for use as repeaters. Other LVDS devices with similar IO characteristics include the following: DS25BR120 functionally optimized drivers use four levels of pre-emphasis, while DS25BR110 functions are used as four levels of equalization for optimized receiving devices. DS25BR150 is a buffer/repeater with the lowest power consumption and functions that do not transmit pre-emphasis or receive equalization.
The wide input common-mode range can accept LVDS, CML, and LVPECL level signals with an output level of LVDS. A very small package size requires minimal space on the board, and flow-through pins allow board design work to be made easier. The differential inputs and outputs of DS25BR100 chip are internally terminated with a 100Ω resistor to reduce return loss, reduce component count, and further reduce board space. In order to increase design flexibility, the DS25BR101 100Ω input terminals have been phased out. This enables the termination of design custom interconnected topologies and layout adjustments.
apply
- Clock and data buffering
- Metal cable drive and equalization
- FR - 4 Equalization
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