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DS32ELX0124SQX
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DS32ELX0124SQX

  • Category:Serializer-deserializer
  • Product Name:125 MHz - 312.5 MHz FPGA - Link deserializer
  • Manufacturers:NSC
  • Production Batch Number:10+
  • Encapsulation:LLP
  • Stock Status:There is stock
  • Stock Quantity:2000
  • Minimum order quantity: 1
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  • Product introduction

peculiarity

  • 5-bit DDR LVDS parallel data interface
  • Programmable receive equalization
  • Optional DC balanced decoder
  • You can choose to add German and scramble
  • Remote sensing automatic detection and link status negotiation
  • There is no need for a reference clock required by an external receiver
  • LVDS parallel interface
  • Programmable LVDS output clock delay
  • Supports output data valid signals
  • Supports keep-alive clock output
  • In the Legislative Council of the chip and VCO
  • Redundant serial inputs (ELX devices only)
  • Retimed serial output (ELX devices only)
  • Configured PLL loop bandwidth
  • Available through SMBus,
  • Lock and error reporting losses
  • 48-pin LLP package exposing diammonium phosphate

illustrate

DS32EL0124 / DS32ELX0124 FR-4 printed circuit board backplane of the clock and data recovery module with integrated high-speed serial communication, balanced cable, optical fiber. This easy-to-use chipset integrates advanced signal and clock regulation functions, is user-friendly, and features an FPGA.

The DS32EL0124/DS32ELX0124 are deserialized at a high speed of 3.125 Gbps to 5 without the need for an external reference clock for LVDS output serial data. With DC balanced decoding enabled, the deserialized application payload is 2.5 Gbps 4 LVDS outputs.

The DS32EL0124/DS32ELX01214 deserializers feature a remote detection function that automatically signals the serialization of their companions DS32EL0421/ELX0421 without additional feedback path for link-state conditions.

The parallel LVDS interface for these devices reduces the FPGA I / O Pins, board trace count, and EMI mitigation issues compared to traditional single-ended wide bus interfaces.

The DS32EL0124/ELX0124 are programmable through the SMBus interface and through the control pin.

Main specifications

  • Serial data rates from 1.25 to 3.125 Gbps
  • DDR parallel clock from 125 to 312.5 MHz
  • -40°C to +85°C temperature range
  • > 8 kV ESD (HBM) protection
  • 0.5 minimum input jitter tolerance for the user interface (1.25 Gbps)


apply

  • Imaging: Industrial, Medical, Printer
  • Display: LED wall, commercial
  • Video transmission
  • Communication systems
  • Test & Measurement
  • Industrial bus

andDS32ELX0124SQXRelated ICs are:


Model Manufacturers lot number encapsulation illustrate
DS32EL0124SQX NSC 10+ LLP 125 - 312.5 MHz FPGA - Link's DDR LVDS parallel interface serializer
DS32ELX0124SQX NSC 10+ LLP 125 MHz - 312.5 MHz FPGA - Link deserializer

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