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DS32ELX0124SQX
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DS32ELX0124SQX

  • 所属类别:串行器-解串器
  • 产品名称:125兆赫- 312.5 MHz的FPGA - Link的解串器
  • 厂商:NSC
  • 生产批号:10+
  • 封装:LLP
  • 库存状态:有库存
  • 库存量:2000
  • 最低订购量:1
  • 详细资料:点击查找DS32ELX0124SQX的pdf资料
  • 点击询价
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  • Product Introduction

peculiarity

  • 5-bit DDR LVDS parallel data interface
  • Programmable reception equalization
  • Optional DC balanced decoder
  • You can choose virtue and disturbance
  • Remote Sensing Automatic Detection and Negotiation of Link Status
  • No reference clock required for an external receiver is required
  • LVDS parallel interface
  • Programmable LVDS output clock delay
  • Support output data valid signal
  • Supports clock output that stays active
  • in the Legislative Council and the VCO of the chip
  • Redundant Serial Inputs (ELX Devices Only)
  • Retiming Serial Output (ELX Devices Only)
  • The configured PLL loop bandwidth
  • Available via SMBus,
  • Locks and errors report losses
  • 48-pin LLP package with exposed diammonium phosphate

illustrate

DS32EL0124 / DS32ELX0124 Integrated clock and data recovery module for high-speed serial communication FR-4 printed circuit board backplane, balanced cable, fiber optics. This easy-to-use chipset integrates advanced signal and clock regulation features a user-friendly interface and features an FPGA.

DS32EL0124/DS32ELX0124 deserialization to serial data at high speeds of 3.125 Gbps up to 5 without the need for LVDS output from an external reference clock. With DC balanced decoding enabled, the deserialized application payload is 2.5 Gbps 4 LVDS outputs.

DS32EL0124/DS32ELX01214 deserializer features remote detection capabilities, automatic signal serialization of its companion DS32EL0421/ELX0421 without additional feedback path conditions of link state.

The parallel LVDS interface of these devices reduces the FPGA I / O pins, board traces and mitigation of EMI issues compared to traditional single-ended wide bus interfaces.

The DS32EL0124/ELX0124 is programmable via the SMBus interface and via the control pins.

Key specifications:

  • Serial data rates from 1.25 to 3.125 Gbps
  • DDR parallel clocks from 125 to 312.5 MHz
  • -40°C to +85°C temperature range
  • > 8 kV ESD (HBM) protection
  • 0.5 minimum input jitter tolerance for user interface (1.25 Gbps)


apply

  • Image: Industrial, Medicare, Printer
  • Display: LED wall, commercial
  • Video transmission
  • Communication system
  • Test & Measurement
  • Industrial bus

DS32ELX0124SQX-related ICs include:


Model Manufacturers lot number encapsulation illustrate
DS32EL0124SQX NSC 10+ LLP 125 - 312.5 MHz FPGA-Link DDR LVDS Parallel Interface Serializer
DS32ELX0124SQX NSC 10+ LLP 125 MHz - 312.5 MHz FPGA - Link deserializer

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