DS32ELX0421SQ

• 5-bit DDR LVDS parallel data interface
• Programmable send de-weighting
• Configurable Output Levels (V OD)
• Selectable DC-balanced encoder
• Data scrambler optional
• Remote Sensing Automatic Detection and Negotiation of Link Status
• in the Legislative Council and the VCO of the chip
• Redundant Serial Outputs (ELX Devices Only)
• Data valid signal to assist in synchronization of multiple receivers
• Supports AC and DC coupled signals
• Terminals that integrate CML and LVDS
• The configured PLL loop bandwidth
• Programmable output terminals (50Ω or 75Ω).
• Built-in test pattern generator
• Locks and errors report losses
• Available via SMBus,
• 48-pin LLP package with exposed diammonium phosphate

illustrate

“ DS32EL0421 / DS32ELX0421 It is a 125 MHz to 312.5 MHz (DDR) high-speed serial transmission ratio FR-4 printed circuit board backplane, balanced cable, fiber optic with FR-4 printed circuit board. This easy-to-use chipset integrates advanced signal and clock regulation features a user-friendly interface and features an FPGA.

DS32EL0421/DS32ELX0421 serialize 5 parallel input LVDS channels to create a payload of up to 3.125 Gbps of data. If integrated DC balanced encoding is enabled, the maximum data payload can be achieved at 2.5 Gbps.

DS32EL0421/DS32ELX0421 serialization capabilities, remote sensing, auto-detection and negotiation DS32EL0124/DS32ELX0124 deserializer with its companions without additional feedback on the path link state.

The parallel LVDS interface reduces the number of I/O pins, board traces and mitigates EMI issues of the FPGA compared to traditional single-ended wide bus interfaces.

DS32EL0421/DS32ELX0421 is programmable via the SMBus interface and via the control pins.

Key specifications:

• Serial data rates from 1.25 to 3.125 Gbps
• DDR parallel clocks from 125 to 312.5 MHz
• -40°C to +85°C temperature range
• > 8 kV ESD (HBM) protection
• Very low intrinsic jitter - 35ps 3.125 Gbps