- 5-bit DDR LVDS parallel data interface
- Programmable send de-emphasis
- Configurable output level (VOD）
- Optional DC balanced encoder
- Data scrambler optional
- Remote sensing automatic detection and link status negotiation
- In the Legislative Council of the chip and VCO
- Redundant serial output (ELX devices only)
- Data valid signals to assist in the synchronization of multiple receivers
- Supports AC and DC coupled signals
- Terminals that integrate CML and LVDS
- Configured PLL loop bandwidth
- Programmable output termination (50Ω or 75Ω).
- Built-in test pattern generator
- Lock and error reporting losses
- Available through SMBus,
- 48-pin LLP package exposing diammonium phosphate
illustrate
“ DS32EL0421 / DS32ELX0421 It is a 125 MHz to 312.5 MHz (DDR) high-speed serial transmission ratio to the backplane of the serializer FR-4 printed circuit board, balanced cable, optical fiber. This easy-to-use chipset integrates advanced signal and clock regulation functions, is user-friendly, and features an FPGA.
The DS32EL0421/DS32ELX0421 serializes 5 parallel input LVDS lanes, creating a maximum payload of 3.125 Gbps of data. If integrated DC balanced encoding is enabled, a maximum data payload of 2.5 Gbps can be achieved.
The serialization capability of the DS32EL0421/DS32ELX0421 enables remote sensing, automatic detection and negotiation of the DS32EL0124/DS32ELX0124 deserializer with its companion without additional feedback on the link status of the path.
The parallel LVDS interface reduces the FPGA's I/O pins, board trace count, and EMI issues compared to traditional single-ended wide-bus interfaces.
The DS32EL0421/DS32ELX0421 are programmable through the SMBus interface and through the control pin.
Main specifications
- Serial data rates from 1.25 to 3.125 Gbps
- DDR parallel clock from 125 to 312.5 MHz
- -40°C to +85°C temperature range
- > 8 kV ESD (HBM) protection
- Very low intrinsic jitter - 35ps 3.125 Gbps
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