DS50PCI401SQ

• PCIe for input and output signal conditioning reaches an increased backplane and cables
• 0.09 after 42" FR4" 5Gbps user interface in residual deterministic jitter (input EQ)
• 0.11 7 m 5Gbps PCIe cable residual deterministic jitter after UI (equalization with input)
• 0.09 UI up to 5Gbps FR4 28" Residual Deterministic Jitter (Output Away)
• 0.13 UI with PCIe cable 7m 5Gbps residual deterministic jitter (output out)
• Adjustable transmission VOD from 800 to 1200mVp-P
• Automatic power management via SMBus on a lane-by-lane basis
• Adjustable electrical idle detection threshold.
• The data transfer rate is optimized with 3 stages of equalization and 26 dB gain
• Optimized data rate level 6, 0 to 12 dB emission deaggravation
• Stream Pass-Through 10mmx5.5mm Leader 54-Pin Leadless LLP Package
• Operates from a single 2.5V supply
• > 6KV HBM ESD rating
• -10 to 85°C operating temperature range

illustrate

DS50PCI401 is a low-power, 4-lane bidirectional buffer/equalizer designed for PCI Express Gen1 and Gen2 applications. The device performs receive equalization and transmit de-emphasis for maximum flexibility, allowing for physical locations within a system. The receiver is open to the input and the eyes are completely closed due to intersymbol interference (ISI) caused by the interconnect medium.

The user can de-emphasize the level based on the distance from the DS50PCI401 to the PCI Express endpoint. DS50PCI401 includes PCI Express-specific features such as send idle receive detection, and beacon signal pass-through.

The device will change the load impedance on the basis of its input pin RXDETA/B input state detection. An IRR detection circuit includes detection if the incoming data stream is in the second generation of data transfer rate, and adjusts its output to de-aggravate accordingly. Signal conditioning provided by the devices allows the system upgrade not to reduce their body data transfer rate from the first generation to the second generation. This is where the real FR4 applies such as backplanes, as well as cable interconnects.