peculiarity
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5 MHz, 35 MHz clock embedding and DC balanced 24:1 and 1:24 data transmission
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User-defined pre-emphasized drive capability via external resistor LVDS output and capability to drive up to 10 meters of shielded twisted pair cable
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User-selectable clock edge transmitter and receive parallel data
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Internal DC-balanced encoding/decoding - Supports an AC-coupled interface without external coding
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Personal power-down control transmitter and reception
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CDR (clock and data recovery) of embedded clocks is received and no external source of reference clock is required
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All code RDL (Random Data Lock) to support field-pluggable applications
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The LOCK output flag is flagged to ensure data integrity at the receiving end
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Balance T
SETUP
/ T
Hold
RCLK and RDATA between receivers
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PTO (step-on) LVCMOS output to reduce EMI and minimize the effects of SSO
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All LVCMOS input and control pins are internally pulled down
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Filters on the transmitter and receiver PLL chips
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Temperature range: -40 °C to +105 °C
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Greater than 8 kV HBM ESD tolerance
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AEC - Q100 compliant
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Supply voltage range: 3.3V ± 10%
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48-pin TQFP package
illustrate
The DS90C241/DS90C124 chipsets convert a fully transparent data/control 24-bit parallel bus with an LVDS serial data stream with embedded clock information.
This single serial data stream simplifies the transmission of PCB traces and cables by eliminating skew issues between parallel data and clock paths, and transporting 24-bit buses.
It saves system cost and shrinks the data path, which reduces the PCB layers, cable width, and connector size and pins.
The DS90C241/DS90C124 use LVDS high-speed I/O signals
LVDS provides a low-power and low-noise environment for reliably transmitting data through the serial transmission path.
By optimizing the serializer output edge rate, EMI over the operating frequency range is further reduced.
In addition, the device has a pre-emphasized signal to increase the distance to lossy cables that are no longer used.
Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects.