DS90C241QVS

• Product Introduction

 peculiarity   5 MHz, 35 MHz clock embedding and DC balanced 24:1 and 1:24 data transmission User-defined pre-weighted drive capability via external resistive LVDS output and capability to drive up to 10 meters shielded twisted pair cable User-selectable clock edge transmitter and receive parallel data Internal DC Balanced Coding/Decoding - Supports AC coupled interfaces without external coding Personal power-down controls transmitter and reception CDR (Clock and Data Recovery) for embedded clocks receives and does not require an external source for reference clocks All code RDL (Random Data Lock) to support field pluggable applications LOCK output flag to ensure data integrity, on the receiving end Equilibrium T SETUP / T holds RCLK and RDATA between recipients PTO (step-by-step) LVCMOS output to reduce EMI and minimize the impact of SSO All LVCMOS inputs and control pins are pulled down inside Filters on the transmitter and receiver phase-locked loop chips Temperature range: -40°C to +105°C Tolerance greater than 8 kV HBM ESD AEC - Q100 compliant Supply voltage range: 3.3V ± 10% 48-pin TQFP package   illustrate The DS90C241/DS90C124 chipset converts into a fully transparent 24-bit parallel bus for LVDS serial data streams with fully transparent data/control with embedded clock information. This single serial data stream simplifies the transmission of PCB traces and cables over the 24-bit bus by eliminating the problem of bias between parallel data and clock paths. It saves system costs and narrows the data path, which reduces the size and pins of PCB layers, cable widths, and connectors. DS90C241/DS90C124 uses LVDS high-speed I/O signals LVDS provides a low-power and low-noise environment for reliable data transmission over serial transmission paths. By optimizing the serializer output edge rate, the operating frequency range EMI is further reduced.   In addition, the device has a pre-emphasis on signals that increase the distance to where the lossy cable is no longer in use. Internal DC balanced encoding/decoding is used to support AC-coupled interconnects.