DS90C383BMT

• There are no special boot sequences between the clock/data and /PD pins that are required. Input signals (clock and data) can be used to power the device before or after.
• Supports spread spectrum clock modulation frequencies up to 100kHz ± 2.5% and propagation center deviation or -5% downspread.
• The "Input Clock Detection" function double-pulls all LVDS to logic low input clocks when missing when the pin of the /PD is logic high.
• Shift clock support from 18 to 68 MHz
• The most advanced settings and hold times on TxINPUTs
• Transmit power consumption
• BiCMOS replacement with more than 40% lower power consumption
• Transmit power saving mode
• Supports dual pixels for VGA, SVGA, XGA and SXGA.
• Narrow bus cable size and cost reduction
• Up to 1.8 Gbps throughput
• Up to 227 MB/s bandwidth
• 345 millivolts (typical) LVDS oscillating device with low electromagnetic interference
• PLL requires no external components
• Compatible with TIA/EIA-644 LVDS standards
• Low-profile 56-pin TSSOP package
• Replacement improvements: SN75LVDS83, DS90C383A

illustrate

The DS90C383B transmitter converts four LVDS (low voltage differential signaling) data stream 28 CMOS/TTL data bits. The phase-locked transmit clock is transmitted in parallel with the fifth LVDS link stream. Transmits 28 bits of input data sampling and transmission per clock cycle. In a transmission of 65 MHz clock frequency, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY bits) are transmitted per 455 Mbps rate of LVDS data channel. With a 65 MHz clock, the data throughput is 227 megabytes per second. The DS90C383B transmitter can be programmed to Rising to strobe via dedicated pin edge or falling edge strobe. The rising or falling edge strobe transmitter will interoperate the falling edge strobe receiver (DS90CF386) without any conversion logic.

This chipset is an ideal means to solve problems related to EMI and cable size, wide and high speed TTL interfaces.