DS90C385AMTX

• Pin-to-pin compatible, DS90C383, DS90C385 DS90C383A, and .
• There are no special pins that require clock/data and /PD between the boot sequences. The input signals (clock and data) can be used to power the device before or after.
• It supports spread spectrum clock modulation frequency up to 100kHz ± 2.5% and propagation center deviation or -5% downward spread.
• The "Input Clock Detection" function will double pull all LVDS to the logic low input clock when the /PD pin is logic high.
• 18 to 87.5 MHz shift clock support
• 发射功率消耗
• Tx功率模式下
• Supports VGA, SVGA, XGA, SXGA (Dual Pixel), SXGA+ (Dual Pixel), up to UXGA (Dual Pixel).
• Narrow bus cable size and reduced cost
• Up to 2.45 Gbps throughput
• The bandwidth is up to 306.25 Megabytes/sec
• 345 mV (typical) LVDS swing device with low electromagnetic interference
• PLLs require no external components
• Compatible with TIA/EIA-644 LVDS standards
• Low-profile 56-pin TSSOP package

illustrate

The DS90C385A is a PIN to PIN DS90C383, DS90C385 DS90C383A, and compatible alternative. The DS90C385A has additional features and improvements that make it an ideal alternative for DS90C383, DS90C385 DS90C383A. LVDS transmitter for homes.

The DS90C385A transmitter converts into 28 LVCMOS/LVTTL data bits for 4 LVDS (Low Voltage Differential Signaling) data streams. A fifth LVDS link stream is transmitted in parallel with the clock and data. 28 bits of input data are transmitted per clock cycle for sampling and transmission. The transmission clock frequency is 87.5 MHz, 24-bit RGB data and 3 LCD timing and control data (FPLINE, FFFRAME, DRDY bits) are transmitted at each 612.5Mbps LVDS data channel rate. Using an 87.5 MHz clock, the data throughput is 306.25 Mbytes/sec. The transmitter can be programmed to rise edge, strobe or descend edge strobe via a dedicated pin. The rising edge or falling edge strobe transmitter will intercommunicate the falling edge to receive any conversion logic from the flicker-free FPDLink.

This chipset is an ideal means to solve the problems associated with EMI and cable size with a wide, high-speed TTL interface that will spread the spectrum clock.