DS90C387RVJD

• Compliant and open LDI digital display interface
• 25 to 85MHz clock support
• Supports VGA to UXGA panel resolutions
• Up to 4.76Gbps dual 24-bit RGB to apply dual pixel bandwidth.
• Dual 12-digit dual pump input domestic violence ordinance ports.
• Pre-weighting reduces cable load effects.
• Long drive and low cost cable
• The transmission of DC balance data is provided by the transmitter Tri-Service Intelligence Agency to reduce distortion
• Transmitter rejects cycle to period jitter. (+/- Input bit period is 2ns)
• Supports both LVTTL and low-voltage level inputs (1.0 to 1.8V capability)
• Two-wire serial communication interface up to 400 kHz
• Programmable input clock and control gate selection
• Backward compatible configuration with 112MHz LDL and FPD links.
• An optional second LVDS clock is available for backward compatibility with the Watt/Flat Panel Display Link receiver
• Compatible with TIA/EIA-644

illustrate

The purpose of this DS90C387R launch is to support the transfer of pixel data from the host to the flat panel display up to UXGA resolution. It is intended to be compatible with the Graphics Memory Controller Hub (GMCH) by implementing every two clock data and can be controlled via a two-wire serial communication interface. Support for two input modes: 12-bit (per clock data) for one port for 24-bit RGB input, and dual 24-bit RGB (48-bit total input) for both ports (12-bit (per clock data). In both modes, the input data will be at the rising edge of the clock and the operating level falling at the LVTTL edge, or over the operating at the low swing differential clock signal across clocks. Clock period with 1/2 width of each input data. With input clocks of input data at 85MHz and 170Mbps, the maximum transfer rate per LVDS line is 595Mbps for a total throughput of 2.38Gbps/4.76Gbps. It can convert 24/48-bit (single/dual pixel 24-bit color) data streams with 4/8 LVDS (Low Voltage Differential Signaling) data streams. DS90C387R can be programmed via a two-wire serial communication interface. The LVDS output pins output the same DS90C387. Therefore, this transmitter can be paired with a DS90CF388,112MHz LDL chipset or a choice of operating between the motherboard manufacturers of the GUI/LCD panel/receiver provided by the Plane Display Link Receiver in non-DC balanced mode with the LVDS TFT board.

DS90C387R also comes with DS90C387 discovery features. The cable driver is reinforced with user-selected pre-emphasis to provide additional output current during transition to counteract cable load effects. DC balancing is on a cycle-to-period basis, also to reduce (inter-symbol interference) and control signals (VSYNC, DE) sent during blanking intervals. With pre-emphasis and DC balancing, the low-distortion eye diagram is provided with the receiving end of the cable. These improvements make the cable between 5 and 15 meters long + depending on the media characteristics and pixel clock speed. Pre-emphasis can be used in both DC and non-DC balanced modes. In non-DC balanced mode, the flat surface and receiver are compatible and linked.

The chip is an ideal solution to address EMI and cable size issues in high-definition flat panel display applications. It provides a reliable industry-standard interface LVDS technology that provides the highest resolution panels need while maximizing the bandwidth required by the same bit, keeping the clock frequency low to reduce electromagnetic interference and shielding requirements. For more details, see the "Application Information" section of this datasheet.