DS90CF364AMTDX

• Shift clock support from 20 to 65 MHz
• 50% receiver output clock duty cycle
• The most advanced settings and hold times on RxOUTPUTs
• RX power consumption
• Receive power-down mode
• ESD rating> 7 kilovolts (HBM), > 700V (EIAJ)
• Supports dual pixels for VGA, SVGA, XGA and SXGA.
• PLL requires no external components
• Compatible with TIA/EIA-644 LVDS standards
• Low-profile 56-pin or 48-pin packages

illustrate

The DS90CF384A 4 LVDS receivers convert data streams (up to 1.8 Gbps throughput or 227 MB/s bandwidth) to 28 parallel CMOS/TTL data bits (24-bit RGB and 4 horizontal sync, v-sync, DE and CNTL bits). It also provides the DS90CF364A conversion of three LVDS streams (up to 1.3 Gbps throughput or 170 megabytes/sec bandwidth) into parallel CMOS/TTL data bits (18-bit RGB and 3 horizontal sync, v-sync, and DE bits). Both receivers' falling edge output strobes. The rising or falling edge gating (DS90C383A/DS90C363A) interoperates with a falling edge without any conversion logic to the strobe receiver.

The DS90CF384A/DS90CF364A devices enhance the previous generation receiver and provide a wider output valid time on the data receiver.

This chipset is an ideal means to solve problems related to EMI and cable size, wide and high speed TTL interfaces.