DS90CF364AMTDX

• Shift clock support from 20 to 65 MHz
• 50% of the receiver output clock duty cycle
• The most advanced settings and hold time on RxOUTPUTs
• RX功率消耗
• 接收掉电模式
• ESD Rating> 7kV (HBM), > 700V (EIAJ)
• Dual Pixel with support for VGA, SVGA, XGA and SXGA.
• PLLs require no external components
• Compliant with TIA/EIA-644 LVDS standard
• Low-profile 56-pin or 48-pin packages

illustrate

The DS90CF384A 4 LVDS receivers convert into data streams (up to 1.8 Gbps throughput or 227 MB/s bandwidth) 28 parallel CMOS/TTL data bits (24-bit RGB and 4 horizontally synced, v-sync, DE and CNTL bits). It also provides DS90CF364A conversion into three LVDS data streams (up to 1.3 Gbps throughput or 170 MB/s bandwidth) 21st times in parallel CMOS/TTL data bits (18-bit RGB and 3 horizontal sync, vertical sync and DE bits). The two receivers' drop edge output gating. Interoperability of a rising or falling edge strobe (DS90C383A/DS90C363A) with a falling edge without any conversion logic strobe receiver.

The DS90CF384A/DS90CF364A device strengthens the previous generation receiver and provides a wider output time-to-hours on the data receiver.

This chipset is an ideal means to solve problems related to EMI and TTL interfaces with cable size, width, high rotational speed.