DS90CF384AMTDX

• Product Introduction

peculiarity

20至65 MHz的移位时钟支持
接收机输出时钟占空比50％
中最佳的类设置及保持RxOUTPUTs时报
接收功耗 接收掉电模式 ESD额定值> 7千伏（HBM）> 700V（EIAJ）
支持VGA，SVGA，XGA和双像素的SXGA。
PLL无需外部元件
TIA/EIA-644 LVDS标准的兼容
薄型56引脚或48引脚封装

illustrate

DS90CF384A receive 4 LVDS data streams (up to 1.8 Gbps throughput or 227 megabytes per second bandwidth) in parallel to convert CMOS/TTL data (24-bit RGB, HSYNC, VSYNC, DE and CNTL and 4-bit) to CMOS/TTL data. It also provides three sets of LVDS data streams (up to 1.3 Gbps throughput or 170 megabytes per second bandwidth) converted into parallel 21-bit CMOS/TTL data (18-bit RGB, HSYNC, VSYNC and DE and 3-bit) (up to 1.3 Gbps throughput or DS90CF364A 170 megabytes per second bandwidth). The two receiver outputs drop along the strobe. Interoperability of a rising or falling edge strobe transmitter (DS90C383A/DS90C363A) with a falling edge strobe receiver does not require any conversion logic.

DS90CF384A/DS90CF364A devices enhance the output of the previous generation receiver and receiver to provide a wider effective time for data.

This chipset is an ideal means to solve problems related to EMI and wide-cable, high-speed TTL interfaces.