DS90CF384MTDX

• Product Introduction

peculiarity

20至65 MHz的移位时钟支持
可编程变送器（DS90C383）频闪选择（上升或下降边缘频闪）
单3.3V电源
芯片组（TX + RX）功耗 掉电模式（ 单个像素每时钟的XGA（1024 × 768）的准备
支持VGA，SVGA，XGA和更高的寻址能力。
高达227兆字节/秒的带宽
高达1.8 Gbps的吞吐量
窄总线减少了电缆的尺寸和成本
290 mV的摆动LVDS器件具有低EMI
PLL无需外部元件
薄型56引脚TSSOP封装。
也可在64球，0.8毫米细间距球栅阵列（FBGA）封装
下降沿数据选通接收器
TIA/EIA-644 LVDS标准的兼容
> 7千伏ESD额定值。
工作温度：-40 ° C至+85 ° C

illustrate

DS90C383 transmitter converts 28-bit LVCMOS/LVTTL data to 4 LVDS (Low Voltage Differential Signaling) data streams. A phase-locked send clock is the parallel data streaming of more than one-fifth of the LVDS links. For each transmit clock cycle, 28-bit input data is sampled and transmitted. DS90CF384 the receiver's LVDS data stream is converted to 28-bit LVCMOS/LVTTL data. Transmit clock frequencies at 65 MHz, 24-bit RGB data and 3-bit LCD timing and control data (FPLINE, FPFRAME, DRDY) at 455 Mbps per LVDS data channel speed. It uses a 65 MHz clock and has a data throughput of 227 MB/s. The transmitter provides programmable edge data gating, convenient interfaces, and a variety of graphics controllers. The transmitter can be programmed to strobe along the rising edge or strobe at the falling edge, via a dedicated pin. The rising edge transmitter interoperable conversion logic does not have any falling edge receiver (DS90CF384). The devices are also available in a 64-ball, 0.8 mm fine-pitch ball grid array (FBGA) package with a 44% reduction in PCB area compared to TSSOP packages.

This chipset is an ideal means to solve problems related to EMI and wide-cable, high-speed TTL interfaces.