- Shift clock support from 20 to 85 MHz
- RX功率消耗
- 接收掉电模式
- ESD Rating> 7kV (HBM), > 700V (EIAJ)
- Supports single pixels in VGA, SVGA, XGA and SXGA.
- PLLs require no external components
- Compliant with TIA/EIA-644 LVDS standard
- Low-profile 56-pin or 48-pin TSSOP packages
- DS90CF386 is also available in a 64-ball, 0.8mm fine-pitch ball grid array (FBGA) package
illustrate
The DS90CF386 4 LVDS receivers convert into data streams (up to 2.38 Gbps throughput or 2975 MB/s bandwidth) 28 times parallel CMOS/TTL data bits (24-bit RGB and 4 horizontally synced, vertically synced, DE and CNTL bits). It also provides DS90CF366 conversion into three LVDS streams (up to 1.78 Gbps throughput or 223 MB/s bandwidth) into 21 parallel CMOS/TTL bits (18-bit RGB and 3 horizontal sync, vertical sync and DE bits). The two receivers' drop edge output gating. Interoperability of a rising or falling edge gutter (DS90C385/DS90C365) with a falling edge without any conversion logic strobe receiver.
The DS90CF386 is also available in a 64-ball, 0.8mm fine-pitch ball grid array (FBGA) package, providing a 44% reduction in printed circuit board space compared to a 56L TSSOP package.
This chipset is an ideal means to solve problems related to EMI and TTL interfaces with cable size, width, high rotational speed.
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