DS90CR217MTDX

• Shift clock support from 20 to 85 MHz
• Receiver output clock duty cycle 50%
• The best class settings and keep TxINPUTs in the time
• Low power consumption
• ± 1V common mode range (approx. +1.2 V)
• The narrow bus reduces the size and cost of the cable
• Throughput up to 1.785 Gbps
• 223 megabytes per second of bandwidth
• 345 mV (typical) low EMI for swinging LVDS devices
• PLLs do not require external components
• The rising edge data is sent
• Compatible with TIA/EIA-644 LVDS standards
• Low-profile 48-pin TSSOP package

illustrate

DS90CR217 transmitter 21-bit CMOS/TTL data is converted into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked send clock is transmitted simultaneously with the fourth LVDS link data stream. Every transmit clock cycle, 21-bit input data is sampled and transmitted. At a transmit clock frequency of 85 MHz, 21-bit TTL data transmission is transmitted at 595 Mbps per LVDS data channel speed. With an 85 MHz clock, the data throughput is 1.785 Gbit/s (223 MB/s).

The narrow bus and LVDS signal DS90CR217 is an ideal means to solve EMI and the problems associated with wide cable size, high-speed TTL interfaces.