DS90CR285MTD

• +3.3 V single power supply
• 芯片组（发送+接收）消耗功率
• 掉电模式“（
• Up to 231 MB/s bandwidth
• Data throughput up to 1.848 Gbps
• Narrow bus cable size is reduced
• Low EMI for 290 mV oscillating LVDS devices
• 1 V common mode range (about 1.2 V).
• PLLs require no external components
• Both devices are available in a low-profile 56-pin TSSOP package
• Data slips through the rising edge of the pulse
• Compliant with TIA/EIA-644 LVDS standard
• ESD rating> 7 thousand volts
• Operating temperature: -40°C to +85°C

illustrate

The DS90CR285 transmitter converts into 28 LVCMOS/LVTTL data bits for 4 LVDS (Low Voltage Differential Signaling) data streams. A fifth LVDS link stream is transmitted in parallel with the clock and data. 28 bits of input data are transmitted per clock cycle for sampling and transmission. The receiver's DS90CR286 LVDS data stream is converted back to 28 LVCMOS/LVTTL data bits. A 66 MHz clock frequency, 28-bit TTL data is transmitted on each LVDS data channel at a rate of 462 Mbps. With a 66 MHz clock, the data throughput is 1.848 Gbit/s (231 megabytes/s).

Cable multiplexing provides significant cable reduction. Long-distance parallel single-ended buses usually need to be ground on each positive signal (and have very limited noise suppression capabilities). Therefore, for a 28-bit wide data and a clock, up to 58 conductors are required. With the channel link chipset 11 fewer wires (4 data pairs, a pair of clocks and a minimum of one place) is necessary. This provides a wide required cable, which provides an 80% reduction in system cost, a reduction in the physical size and cost of connectors, and a smaller size of the cable due to shielding requirements.

28 LVCMOS/LVTTL inputs can support a combination of multiple signals. For example, seven 4-bit half-bytes or three 9-bit (bytes + checksum) and 1 control.