- Single +3.3 V supply
- The chipset (send + receive) consumes power
- Power-down mode" (
- Up to 231 MB/s bandwidth
- Up to 1.848 Gbps data throughput
- Narrow bus cables are reduced in size
- Low EMI of 290 mV swing LVDS devices
- 1 V common-mode range (approx. 1.2 V).
- PLL requires no external components
- Both devices are available in a thin 56-pin TSSOP package
- Data gating pulse rising edge
- Compatible with TIA/EIA-644 LVDS standards
- ESD rating> 7 kV
- Operating temperature: -40°C to +85°C
illustrate
The DS90CR285 transmitter converts 28 LVCMOS/LVTTL data bits for four LVDS (low voltage differential signaling) data streams. The phase-locked transmit clock is transmitted in parallel with the fifth LVDS link stream. Transmits 28 bits of input data sampling and transmission per clock cycle. The receiver's DS90CR286 LVDS data stream is converted back to 28 LVCMOS/LVTTL data bits. At a transmit clock frequency of 66 MHz, 28-bit TTL data is transmitted over each LVDS data channel at a rate of 462 Mbps. With a clock of 66 MHz, the data throughput is 1.848 Gbit/s (231 megabytes/s).
Data line multiplexing provides a significant reduction in cables. Long-distance parallel single-ended buses typically require ground at each aggressive signal (and have very limited noise suppression capabilities). Therefore, for a 28-bit wide data and a clock, up to 58 conductors are required. With the channel link chipset having 11 fewer wires (4 data pairs, one pair of clocks and one minimum of the ground) is necessary. This provides a wide required cable, which provides an 80% reduction in system cost, reduces the physical size and cost of connectors, and reduces the size of the cable due to shielding requirements.
The 28 LVCMOS/LVTTL inputs support multiple signal combinations. For example, seven 4-bit nibbles or three 9-bits (bytes + checksum) and 1 control.
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