DS90CR288AMTDX

• Product introduction

peculiarity

Shift clock support from 20 to 85 MHz
Receiver output clock duty cycle 50%
2.5/0 NS set and keep TxINPUTS times
Low power consumption
± 1V common-mode range (approximately +1.2 V)
The narrow bus reduces the size and cost of the cable
Up to 2.38 Gbps throughput
Year-over-year increase of 297.5 megabytes per second bandwidth
Low EMI of 345 millivolts (typical) oscillating LVDS devices
The PLL requires no external components
Ascending edge data gating
Compatible with the TIA/EIA-644 LVDS standard
Low profile 56-pin TSSOP package

illustrate

The DS90CR287 transmitter converts 28-bit LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is more than one-fifth of the parallel traffic transmission of the LVDS link. Each transmit clock cycle, 28-bit input data is sampled and transmitted. The DS90CR288A receives four LVDS streams converted to 28-bit LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28-bit TTL data is transmitted at a data channel speed of 595 Mbps per LVDS. Using an 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 MB/s).

This chipset is an ideal solution to issues related to EMI and cable size wide, high-speed TTL interfaces.