DS90CR288AMTDX

• Product Introduction

peculiarity

Shift clock support from 20 to 85 MHz Receiver output clock duty cycle 50% 2.5/0 NS Setting and Maintaining TxINPUTs Timing Low power consumption ± 1V common mode range (approx. +1.2 V) The narrow bus reduces the size and cost of the cable Up to 2.38 Gbps throughput Bandwidth increased by 297.5 megabytes per second year-on-year 345 mV (typical) low EMI for swinging LVDS devices PLLs do not require external components The rising edge data is sent Compatible with TIA/EIA-644 LVDS standards Low-profile 56-pin TSSOP package

illustrate

DS90CR287 transmitter converts 28-bit LVCMOS/LVTTL data into 4 LVDS (Low Voltage Differential Signaling) data streams. A phase-locked send clock is the parallel data streaming of more than one-fifth of the LVDS links. For each transmit clock cycle, 28-bit input data is sampled and transmitted. DS90CR288A 4 LVDS data streams received are converted to 28-bit LVCMOS/LVTTL data. With a transmit clock frequency of 85 MHz, 28-bit TTL data transmission is transmitted at 595 Mbps per LVDS data channel speed. With an 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 MB/s).

This chipset is an ideal means to solve problems related to EMI and wide-cable, high-speed TTL interfaces.