DS90CR485VS

• Up to 6.384 Gbps throughput
• Input clock support from 66MHz to 133MHz
• Reduce the size and cost of cables and connectors
• Pre-emphasis reduces the load effect of the cable
• DC balancing to reduce ISI distortion
• 24-bit dual-force input
• Fault-tolerant 3V LVCMOS/LVTTL input
• Low power consumption, 2.5V power supply
• The flow passes through the leader line
• It is available in a 100-pin TQFP package
• Meets the LVDS standard of TIA/EIA-644-A.

illustrate

DS90CR485 serialized 24 to 8 low-voltage differential signal (LVDS) streams of LVCMOS/LVTTL dual-advantage inputs (48-bit latching data at each clock cycle). The lock-in transmission clock also exceeds the data flow parallelism of the ninth LVDS link. Extensive TTL buses are reduced to several LVDS transmission lines, reducing cable and connector size and cost. The rise and fall on the bilateral input data are gated along the clock. This minimizes the number of pins required and simplifies chip and serial PCB routing between hosts.

The chip is an ideal solution to address EMI and interconnect points to point the size of high-throughput applications.

DS90CR485 is for use with DS90CR486 channel link receivers. It's also backwards compatible with connections with other channels like DS90CR482 and DS90CR484 reception.