DS90LV012ATMF

• Compatible with ANSI TIA/EIA-644-A
• "400 Mbps (200 MHz) switching rate
• 100 ps differential offset (typical)
• 3.5 ns maximum transmission latency
• Integrated Line Termination Resistor (102Ω typical)
• 3.3V Single Supply Design (2.7V to 3.6V Range)
• The power-down LVDS input impedance is high
• Accept a small swing (typical of 350 mV) differential signal level
• LVDS receiver input accepts LVDS/BLVDS/LVPECL input
• Supports open-circuit, short-circuit, and termination input fail-safe
• Pins simplify PCB layout
• Low power consumption (typical@3.3V static at 10mW)
• Available in a SOT-23 5-pin package
• Lead-Free LLP - 8 Package (3x3 mm Body Size)
• Electric similar DS90LV018A
• Equipped with advanced CMOS process technology
• Industrial temperature operating range

• (-40°C to +85°C)

illustrate

should DS90LV012A DS90LT012A is designed for ultra-low power, low-noise applications, and high data rates required by a single CMOS differential line receiver. These devices are designed to support data transfer rates of up to 400 Mbps (200 MHz) using low-voltage differential swing transfer (LVDS) technology

should DS90LV012A and DS90LT012A accept low-voltage (350 mV typical) differential input signals and convert them to the 3V CMOS output level. The receiver also supports open-circuit, short-circuit, and termination (100Ω) input fail-safe. The output of the receiver will be high in all fail-safe conditions. should DS90LV012A It has a pin designed to facilitate PCB layout. should DS90LT012A Includes an input line termination resistor for point-to-point applications.

should DS90LV012A DS90LT012A and Mate LVDS line drivers provide a new alternative to high-speed interfaces for high-power PECL electrical/electrochemiluminescent devices.