DS90LV028ATLD

• > 400 Mbps (200 MHz) switching rate
• 50 PS differential offset (typical)
• 0.1 ns channel to channel skew (typical)
• Maximum propagation latency of 2.5 ns
• 3.3V power supply design
• The flow passes through the leader line
• Lower high-impedance power supply LVDS input
• Low power consumption design (18mW@3.3V static)
• Interoperable networks with existing 5V LVDS
• Accepts small swing (typical of 350 mV) differential signal levels
• Supports open-circuit, short-circuit, and termination input fail-safe
• Compliant with ANSI/TIA/EIA-644 standards
• Industrial temperature operating range (-40 °C to +85 °C)
• Available in SOIC and space-saving LLP packaging

illustrate

This DS90LV028A is a dual CMOS differential line receiver designed for applications requiring ultra-low power consumption, low noise, and high data rates. The device is designed to support data rates exceeding 400 Mbps using Low Voltage Differential Signal (LVDS) technology (200 MHz).

This DS90LV028A receives low-voltage (typical 350 mV) differential input signals and converts them to a 3V CMOS output level. The receiver also supports on, short-circuit, and termination (100 ) input fail-safe. Receiver outputs will be used under all high fail-safe conditions. This DS90LV028A features a simple PCB layout stream-based design.

This DS90LV028A and its companion LVDS line drivers offer a new option for high-power PECL/ECL high-speed point-to-point interface applications.