DS90UB904QSQX

• 10 MHz to 43 MHz input PCLK support
• 903 Mbps data throughput 210 Mbps
• Single differential pair interconnection
• Bidirectional control of the interface channel with I 2 Support C
• Embedded DC-balanced coding supports AC-coupled clock interconnects
• Capable of driving shielded twisted pairs up to 10 meters
• I 2 C-compatible serial interface
• A single hardware device solves the needle
• Up to 4 Universal Inputs (GPIs)/Outputs (GPOs)
• Lock output report pins and AT - speed BIST self-diagnostic to verify link integrity
• Integrated termination resistors
• 1.8V or 3.3V compatible parallel bus interfaces
• Operates from a single 1.8V supply
• ESD to ISO 10605 standard and IEC 61000-4-2 ESD compliant
• Automotive-grade products: AEC - Q100 standard Level 2 qualified
• Temperature range from -40°C to +105°C
• There is no reference clock deserializer
• Programmable reception equalization
• Mitigation of EMI/EMC
• DES's programmable spread spectrum (SSCG) output
• DES receives staggered outputs

illustrate

The DS90UB903Q/DS90UB904Q chipset provides a high-speed forward channel and a linked FPD-III interface for data transfer in a single differential pair bidirectional control channel. The DS90UB903Q/904Q uses differential signals on the data path for both high-speed forward channels and bidirectional control channels. It is a direct connection between the serializer/deserializer to the graphics host controller and the display module. This chipset is ideal for driving video data display, requiring 18-bit color depth (RGB666 + HS, VS, and DE) and a bi-directional control channel bus. The main transmission of 21-bit data is converted into a single high-speed serial data stream, which is transported with a separate low-latency bidirectional control channel to receive my control information 2 C port. Using National Semiconductor's embedded clock technology, it allows for bidirectional asymmetric bidirectional control channel information in a single differential pair of transparent full-duplex communication. This single serial data stream simplifies the transmission of PCB traces and cables to the data bus by eliminating bias issues between parallel data and clock paths. This significantly saves system costs and narrows the data path, reducing the size and pins of PCB layers, cable widths, and connectors.

In addition, the deserializer input provides equalization control from the media over longer distances to compensate for losses. Internal DC balanced encoding/decoding is used to support AC-coupled interconnects.

The serializer is a 40-pin lead in a law firm, and the deserializer is supplied in a 48-pin LLP package.

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• Automotive display systems
• Central information display
• Navigation display
• Backseat entertainment
• Touch screen display