DS90UB904QSQX

• Support for input PCLK from 10 MHz to 43 MHz
• 903 Mbps的数据吞吐量210 Mbps的
• Single differential pair interconnect
• Bidirectional control of the interface channel with I 2 Support C
• Embedded DC balanced coding supports AC-coupled clock interconnects
• Capable of driving shielded twisted pair up to 10 meters
• I 2 C-compatible serial interface
• A single hardware device solves the pin
• 多达4个通用输入（GPI）/输出（GPO）
• The lock output report pin and the AT-speed BIST self-diagnostic function to verify the integrity of the link
• Integrated termination resistors
• 1.8V or 3.3V compatible with parallel bus interface
• Operates from a single 1.8V supply
• The ESD of the ISO 10605 standard is compatible with the ESD of IEC 61000-4-2
• Automotive grade products: AEC - Q100 standard level 2 qualified
• Temperature range -40 °C to +105 °C
• There is no reference clock on the deserializer
• Programmable receive equalization
• EMI/EMC mitigation
• Programmable spread spectrum (SSCG) output of DES
• Receive interleaved output of DES

illustrate

DS90UB903Q/DS90UB904Q芯片组提供了一个高速前进的通道，并在一个单一的差分对双向控制通道的数据传输的一个链接的FPD - III接口。 DS90UB903Q/904Q无论是高速前进的通道和双向控制通道数据路径上采用差分信号。 是针对串行器/解串器对图形主机控制器和显示模块之间的直接连接。 该芯片组是非常适合驾驶视频数据显示，需要18位色彩深度（RGB666 + HS，VS，和DE）以及双向控制通道总线。 主要传输21位数据转换成单一的高速串行数据流，随着一个单独的低延迟双向控制通道的交通运输，接受我的控制信息 2 C端口。 使用美国国家半导体的嵌入式时钟技术，允许在一个单一的差分对透明的全双工通信，进行两个方向非对称双向控制通道信息。 This single serial data stream simplifies the transmission of data buses by eliminating skews between parallel data and clock paths. This results in significant savings in system cost and narrowing the data path, which reduces PCB layers, cable width, and connector size and pins.

In addition, the deserializer input provides equalization control from the media over longer distances to compensate for losses. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects.

序列化程序是在一个律师事务所的40针引线，提供解串器是在一个48引脚的LLP封装提供。

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