DS90UR905QSQE

• 10 MHz to 43 MHz input PCLK support
• Data throughput from 160 Mbps to 688 Mbps
• Single differential pair interconnection
• Bidirectional control of the interface channel with I 2 Support C
• Embedded DC-balanced coding supports AC-coupled clock interconnects
• Capable of driving shielded twisted pairs up to 10 meters
• I 2 C-compatible serial interface
• A single hardware device solves the needle
• The 16-bit data payload CRC (Cyclic Redundancy Check) checks the integrity of the data
• 6 programmable GPIOs
• Lock output report pins and AT - speed BIST self-diagnostic to verify link integrity
• Integrated termination resistors
• 1.8V or 3.3V compatible parallel bus interfaces
• Operates from a single 1.8V supply
• ESD to ISO 10605 standard and IEC 61000-4-2 ESD compliant
• Automotive-grade products: AEC - Q100 standard Level 2 qualified
• Temperature range from -40°C to +105°C
• There is no reference clock deserializer
• Programmable reception equalization
• Mitigation of EMI/EMC
• DES's programmable spread spectrum (SSCG) output
• DES receives staggered outputs

illustrate

The DS90UB901Q/DS90UB902Q chipset provides a high-speed forward channel and a linked FPD-III interface for data transfer in a single differential pair bidirectional control channel. It is a direct connection between the camera system and the host controller/electronic control unit (ECU) of the car for the serializer/deserializer. The main transmission sends 16-bit image data in a single high-speed serial data stream, along with a low-latency bidirectional control channel, supporting my transport 2 C. Contains a 16-bit payload that is an optional data integrity option for CRC (Cyclic Redundancy Check) to monitor transmission link errors. Using national embedded clock technology, which allows for transparent full-duplex communication in a single differential pair, the video blanking interval relies on carrying asymmetric bidirectional control information. This single serial data stream simplifies the transmission of PCB traces and cables to the data bus by eliminating bias issues between parallel data and clock paths. This significantly saves system costs and narrows the data path, reducing the size and pins of PCB layers, cable widths, and connectors.

In addition, the deserializer input provides equalization control from the media over longer distances to compensate for losses. Internal DC balanced encoding/decoding is used to support AC-coupled interconnects.

A serialized standby function provides the ability to wake up remotely with a signal from a remote device in a low-power saving mode.

The serializer is available in a 32-pin LLP (5mm x 5mm) package, and the deserializer is available in a 40-pin LLP (6mm x 6mm) package.

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• Automotive vision systems
• Rear view, side view camera
• Lane departure warning
• Parking Assist
• Blind spot viewing