DS90UR906QSQ

• Input PCLK support from 10 MHz to 43 MHz
• Data throughput from 160 Mbps to 688 Mbps
• Single differential pair interconnection
• Bidirectional control of the I interface channel 2 C support
• Embedded DC-balanced coding supports AC-coupled clock interconnects
• Capable of driving shielded twisted pairs up to 10 meters
• I 2 C compatible with serial interfaces
• Single-pin hardware device addressing
• CRC (Cyclic Redundancy Check) for 16-bit data payloads checks data integrity
• Up to 6 programmable GPIOs
• LOCK pin output reporting and AT-speed BIST self-diagnostics to verify link integrity
• Integrated termination resistors
• 1.8V or 3.3V compatible parallel bus interfaces
• In a single 1.8V supply
• ISO 10605 and IEC 61000-4-2 ESD standards
• Automotive-grade products: AEC - Q100 Level 2 qualified
• Temperature range from -40°C to +105°C
• There is no reference clock that requires a deserializer
• Programmable reception equalization
• EMI/EMC mitigation
• DES Programmable Spread Spectrum (SSCG) output
• DES receives interleaved outputs

illustrate

The DS90UB901Q/DS90UB902Q chipset provides high-speed forward channels and triple interfaces for data transmission bidirectional control channel A FPD-Link via a differential pair. The pairing between the serializer/deserializer is for the direct connection between the automotive camera system and the main controller/electronic control unit (ECU). The main traffic transmits 16-bit image data through a high-speed serial stream with a low-latency bidirectional control channel, supporting me 2 C. Includes a 16-bit payload with an optional data integrity option that monitors errors in the transmission link with CRC (Cyclic Redundancy Check). The use of National Semiconductor's embedded clock technology allows for transparent full-duplex communication in a single differential pair, carrying asymmetric bidirectional control information without video blanking interval dependence. This single serial data stream ratio simplifies the problem of data bus cables within the range of deviations between PCB traces and clock paths between parallel data and clock paths. This significantly saves on shrinking data paths, resulting in lower PCB layers, cable widths, and connector size and pin system costs.

In addition, the deserializer input provides equalization control to compensate for losses due to media over long distances. Internal DC balanced coding/decoding is used to support AC coupled interconnects.

Serialized standby provides up to functional remote device signal remote wake-up low-power saving mode.

The serializer is available in a 32-pin LLP (5× 5mm) package, and the deserializer is available in a 40-pin LLP (6×6mm) package.

apply

• Automotive vision systems
• Rear view, side view camera
• Lane departure warning
• Parking Assist
• Blind spot viewing