DS90UR906QSQE

• Input PCLK support from 10 MHz to 43 MHz
• Data throughput from 160 Mbps to 688 Mbps
• Single differential pair interconnect
• Bidirectional control I-interface channels 2 C support
• Embedded DC balanced coding supports AC-coupled clock interconnects
• Capable of driving shielded twisted pair up to 10 meters
• I 2 C compatible with serial interfaces
• Single-pin hardware device addressing
• CRC (Cyclic Redundancy Check) for 16-bit data payloads checks data integrity
• Up to 6 programmable GPIOs
• LOCK pin-out reports and AT-speed BIST self-diagnostics to verify link integrity
• Integrated termination resistors
• 1.8V or 3.3V compatible with parallel bus interface
• Single 1.8V supply
• ISO 10605 and IEC 61000-4-2 ESD electrostatic discharge standards
• Automotive grade product: AEC - Q100 Class II qualified
• Temperature range -40 °C to +105 °C
• There is no need for a deserializer on the reference clock
• Programmable receive equalization
• EMI/EMC mitigation
• DES programmable spread spectrum (SSCG) output
• DES receives interleaved output

illustrate

The DS90UB901Q/DS90UB902Q chipsets provide a high-speed forward channel and three interfaces for data transmission bidirectional control channel A FPD-Link via a differential pair. The pairing between the serializer/deserializer is for the direct connection of the automotive camera system and the main controller/electronic control unit (ECU). The main traffic is transmitted through a high-speed serial stream of 16-bit image data along with a low-latency bidirectional control channel that supports me 2 C. Included with a 16-bit payload is an optional data integrity option CRC (Cyclic Redundancy Check) to monitor transmission link errors. The use of NIC's embedded clocking technology allows transparent full-duplex communication in a single differential pair, carrying asymmetric bidirectional control information without video blanking intervals. This single serial data stream simplifies PCB traces and eliminates the problem of data bus cables within the range of parallel data and clock path deviations. This results in significant savings in shrinking the data path, which reduces PCB layers, cable width, and connector size and pin system costs.

In addition, the deserializer input provides equalization control to compensate for loss of media over long distances. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects.

The serialized standby feature provides a low-power saving mode for remote wake-up of remote device signals up to function.

The serializer is available in a 32-pin LLP (5 × 5mm) package and the deserializer in a 40-pin LLP (6 × 6mm) package.

apply

• Automotive vision systems
• Rear view, side view camera
• Lane departure warning
• Parking assistance
• Blind spot viewing