DS91D176TMA

• Low power, low EMI operation from DC to 100+ MHz/200+ Mbps
• Optimal ATCA, uTCA clock distribution network
• Meets or exceeds TIA/EIA-899 M - LVDS standards
• To improve noise wide input common-mode voltage immunity
• DS91D176 is a Type 1 receiver input
• The type of DS91C176 and 2 receive fail-safe
• Industrial temperature range
• The space-saving SOIC-8 package is available

illustrate

Transceivers designed using multipoint networks such as ATCA and uTCA-based system clock distribution in applications where the DS91C176 is 100 MHz and DS91D176 single channel M-LVDS (multipoint low voltage differential signaling). M-LVDS is a new bus interface standard (TIA/EIA-899) optimized for multipoint networks. Edge rate control, tight input receiver thresholds and intensity increase lanes of Zen, making M-LVDS devices ideal for distributing network signals through multipoint key enhancments.

The DS91C176/DS91D176 is a half-duplex transceiver that receives the LVTTL/LVCMOS input signal in drive and converts it into a differential M-LVDS signal. The receiver inputs a low-voltage differential signal to receive transmission (LVDS, LVDS of type B, M-LVDS, low voltage, PECL and CML) and convert it to a 3V LVCMOS signal. The DS91D176 has an unoffset M-LVDS receiver input type 1. The DS91C176 has an M-LVDS receiver that enables Type 2 fail-safe functionality.