DS92CK16TMTC

• Backplane clock selection in the master/slave application
• 125 MHz operating frequency (typical)
• 100 ps duty cycle distortion (typical)
• 50 ps channel-to-channel deviation (typical)
• 3.3V power supply design
• The trouble-free power supply is located in the clkI/O pin
• Low-power design (20 mA@3.3V static)
• Accept the small swing (typical value of 300 mV) differential signal level
• Industrial temperature operating range (-40°C to +85°C)
• 24-pin TSSOP package

illustrate

The 1 to 6 DS92CK16 clock buffer/bus transceiver is a one- to six-month CMOS differential clock distribution device that utilizes the bus's low-voltage differential signaling (BLVDS) technology. This clock distribution device is designed for applications that require ultra-low power, low noise, and high data rates. The BLVDS side acts as a separate return/source clock acting channel transceiver.

The DS92CK16 accepts LVDS (typical values of 300 mV) differential input levels and converts them to CMOS output levels of 3V. The output enables pin OE#, when high, forces all clock output pins to be high.

The device can be used as a source synchronization driver. The driver source of choice is controlled by the CrdCLK and DE# pins. The unit can be used as a master clock, driving inputs on other clock I/O pins in a multi-point environment. The choice of the master/slave clock is to implement along the backplane.