DS92CK16TMTCX

• Select the master/slave clock in the backplane application
• 125 MHz operating frequency (typical)
• 100 PS Duty Cycle Distortion (Typical)
• 50 ps channel-to-channel skew (typical)
• 3.3V power supply design
• Interference-free power supply clkI/O pins
• Low-power design (20 mA@3.3V static)
• Accept a small swing (300 mV (typical)) differential signal level
• Industrial operating temperature range (-40°C to +85°C)
• Available in a 24-pin TSSOP package

illustrate

DS92CK16 1 to 6 clock buffer/bus transceiver is a 6 CMOS differential clock distribution device that utilizes the bus's low-voltage differential signaling (BLVDS) technology. This clock distribution device is designed for applications that require ultra-low power, low noise, and high data rates. The BLVDS side is a separate channel that acts as a transceiver for a one-time/clock source.

DS92CK16 accepts (300 mV typical for LVDS) differential input level and converts it to a 3V CMOS output level. The output enable pin OE# is high, when the output pins of all CLKs in the force are high.

The unit can be used for source-synchronized drives. Select the source drive control and the DE# pin CrdCLK. The device can act as a master clock, driving the inputs of the I/O pins of other clocks in multiple environments. The choice of master/slave clock is implemented along the backplane.