- Bus LVDS signaling (BLVDS)
- Designed for double-terminated applications
- Balance the output impedance
- Typical of the Lite bus load 5pF
- Glitch free power, up/down (driver disabled)
- 3.3V or 5.0V operation
- ± 1V common-mode range
- ± 100mV receive sensitivity
- Signaling high rate discharge performance (over 100 Mbps).
- Low-power CMOS design
- The product is available in an 8-lead SOIC package
- Operates over an industrial-grade temperature range
illustrate
The DS92LV010A is one of a special family of dedicated bus backplane interfaces designed for high-speed, low-power transceivers. The device operates from a single 3.3V or 5.0V supply, with a differential line driver and a receiver. To minimize bus loading, the driver output and receiver input are interconnected together. The logic interface provides maximum flexibility, providing 4 separate lines (German DIN standard, de, ^ rare earth, and ROUT). The device also features streams, through which it is easy to route short stubs between bus pins and connectors between printed circuit boards. The driver has a 10 mA drive capability, allowing it to drive a high load backplane with a low impedance of 27 ohms.
Driver with TTL level (single-ended) to low voltage differential signal conversion level. This allows high-speed operation while consuming minimal power to reduce EMI. In addition, the differential signal provides common-mode noise rejection ± 1V.
The receiver threshold is ± ± a common-mode range of 1V and translates 100mV to the standard level of low voltage differential level (CMOS/TTL).
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