DS92LV1021AMSA

• Bus LVDS Signal (BLVDS)
• Designed for double-terminated applications
• Balanced output impedance
• The typical load of Jianxing bus is 5pF
• Power of glitch freedom, up/down (driver disabled)
• 3.3V or 5.0V operation
• ± 1V common mode range
• ± 100mV reception sensitivity
• signaling high rate discharge performance (more than 100 Mbps).
• Low-power CMOS design
• The product is available in an 8-lead SOIC package
• Operates within an industrial grade temperature range

illustrate

This DS92LV010A is part of a special series of transceivers designed for high-speed, low-power dedicated bus backplane interfaces. The device operates from a single 3.3V or 5.0V supply with a differential line driver and a receiver. To minimize bus load, the driver output and receiver input are internally connected. The logic interface provides maximum flexibility, providing 4 separate lines (German DIN standard, German, ^rare earth, and ROUT). The device also features a stream through which bus pins and connector short stub routing are easily printed between circuit boards. The driver has a 10 mA drive capability that allows it to drive a high load backplane with a low impedance of 27 ohms.

Driver with TTL level (single-ended) to low voltage differential signal conversion level. This allows for high-speed operation while consuming minimal power to reduce EMI. In addition, the differential signal provides common-mode noise suppression of ± 1V.

The receiver threshold is ± ± 1V in the common mode range and converts 100mV to the level of the low voltage differential level standard (CMOS/TTL).