DS92LV1021AMSAX

• Guarantee every data transfer cycle of the transition
• Single-differential pairs eliminate multi-channel skew
• The flow through the lead wire facilitates PCB layout
• 400 Mbps serial bus LVDS bandwidth (40 MHz clock)
• 10-bit parallel interface, 1 byte of data plus 2 control bits
• Programmable clock edge triggering
• The bus LVDS serial output is rated at 27 load
• Small 28-pin SSOP package - MSA

illustrate

DS92LV1021A a serial data stream of a high-speed bus LVDS embedded clock is converted into a 10-bit wide parallel LVCMOS/LVTTL data bus. DS92LV1021A can transmit data through a backplane or cable. Single differential pair of data paths to make PCB design easier. In addition, reducing the number of cables, PCB traces, and connector size greatly reduces costs. It eliminates clock-to-data and data-to-data skew thanks to one output serial transmission clock and data bits. The power-down pin saves power supply by reducing the supply current when the device is not in use. After serialization, you can choose to activate the synchronization mode or synchronize the random data function, using a destringency from National Semiconductor. By using synchronous mode, the deserializer will establish a signal that is locked to a specified lock time. In addition, the embedded clock guarantees transitions every 12 digits on the bus. This eliminates transmission errors due to live cable conditions. In addition, you may throw in the TRI - STATE ® DS92LV1021A output pin to achieve a high impedance state. PLLs can lock frequencies between 16 MHz and 40 MHz.