DS92LV1212AMSAX

• Out-of-sync clock recovery mode random lock
• Guaranteed transition every data cycle
• Chipset (send + receive) power consumption
• Single differential pair eliminates multichannel skew
• 400 Mbps serial bus LVDS bandwidth (40 MHz clock)
• 10 bits for one byte of data plus 2 control bits or utopia I interface parallel interface
• Synchronous mode and LOCK indicator
• Flow through the pinout for easy PCB layout
• The receiver input impedance is high when the power is turned off
• Programmable clock edge triggering
• The footprint is compatible with the DS92LV1210
• Small 28-pin SSOP package - MSA

illustrate

The DS92LV1212A is an upgrade to the DS92LV1212. It performs all the functions of the DS92LV1212. The DS92LV1212A is designed for use with the DS92LV1021 bus LVDS serializer. The DS92LV1212A receives an LVDS serial bus data stream and converts it into a 10-bit wide parallel data bus and independent clock. Reducing the number of cables, PCB traces, and connector sizes saves costs and makes PCB layout easier. Clock-to-data and data-to-data skew are eliminated because one or two clock input and receive serial data bits. The power saving pin is not used when used to save equipment by reducing the current power supply. The deserializer establishes a lock in the specified lock time synchronization mode, but it can also lock to a stream without synchronization mode.