DS92LV1212AMSAX

• The out-of-sync clock recovery mode is randomly locked
• Guarantee every data transmission cycle transition
• 芯片组（发送+接收）功耗
• Single-differential pairs eliminate multi-channel skew
• 400 Mbps serial bus LVDS bandwidth (40 MHz clock)
• 10 bits is one byte of data plus 2 control bits or Utopia I interface parallel interface
• Sync mode and LOCK indicator
• Flow through the lead-out lines for easy PCB layout
• When the receiver input impedance is high, when the power is turned off
• Programmable clock edge triggering
• Footprint compatible with DS92LV1210
• Small 28-pin SSOP package - MSA

illustrate

The DS92LV1212A is an upgrade to DS92LV1212. It performs all the functions of the DS92LV1212. The DS92LV1212A is designed to be used with DS92LV1021 bus LVDS serializers. The DS92LV1212A receives an LVDS serial bus stream and converts it into a 10-bit wide parallel data bus with independent clocks. Reducing the size of cables, PCB traces, and connectors saves costs and makes PCB layout easier. Clock-to-data and data-to-data skew are eliminated because one or two clocks input and receive serial data bits. The power saving pin is not used when the saving pin is used to save by reducing the current power supply of equipment. The deserializer will establish a locked synchronization mode at the specified lock time, but it can also lock to a data stream without a synchronization mode.