peculiarity
Single 300-660 MB/s troughput 1:10 deserializer at 66-66 MHz
Le Bai bus LVDS serial data transmission with excellent interference immunity and low EMI with embedded clocks embedded clocks
The clock recovery PLL locks the random data pattern.
Guarantee every data transfer cycle of the transition
Low power consumptionSingle differential pair eliminates multichannel skew
Flow through the lead wires for easy PCB layout
Sync mode and LOCK indicator
Programmable clock edge triggering
When the receiver input is powered off with a high impedance supply
Small 28-pin SSOP package
illustrate
The DS92LV1224 is a 300 to 660 Mb/s high-speed, unidirectional serial ratio FR-4 printed circuit board backplane and balanced copper cable transfer data deserializer. It receives a stream of LVDS serial data from a compatible 10-bit serial bus, converts it into a 10-bit wide parallel data bus, and recovers the parallel clock. This single serial data stream simplifies PCB design, reduces PCB cost, and shrinks data paths, thereby reducing PCB size and layer count. A single serial data stream also reduces the size of cables, the number of connectors, and eliminates clock data and data-data skew.
The DS92LV1224 works as well as a 10-bit serializer operating with any national semiconductor bus LVDS in its specified frequency operating range. It has low power consumption, high power impedance output, power-down mode.
The DS92LV1224 is designed with a flow-through pin and 28-lead SSOP package to save space.