DS92LV3221TVS

• Product Introduction

 peculiarity   Wide operating voltage range Embedded clock SER/DES   Parallel LVCMOS for 32-bit data 20 to 50 MHz parallel clock Up to 1.6 Gbps of application data paylod Simplified clock architecture   There is no separate serial clock line No need to refer to the clock The receiver locks random data Robust on-chip signal conditioning for serial connections   Send a pre-weight Data is random DC balanced coding Receive channel correction At 1.6Gbps, CAT-10 supports up to 5 meters Integrated LVDS terminals Built-in AT-speed BIST self-test from the end of the year to the final system test Isolation and fault protection for AC coupled interconnects > 4KV HBM ESD protection Space-saving 64-pin TQFP package Entire industrial temperature range: -40° to +85°C   illustrate DS92LV3221 (SER)2 embedded clocks have LVDS serial channel data payload rates up to 1.6 Gbps over cables, such as Ca-Protocol, or FR-4 traces serialized into a 32-bit data bus. Deserialization of peer DS92LV3222 (DES)2 LVDS serial data channels, de-skewed channel-to-channel latency variations, and converting them into 32-bit LVCMOS parallel data bus LVDS data streams. On-chip data random/scrambled and DC balanced coding and optional serializer pre-emphasis ensure a robust, low-EMI propagation over long periods of lossy cables and backplanes. The deserializer automatically locks incoming data without the need for an external reference clock or special synchronization mode, providing a simple "plug-in and lock" operation. Channel Link II SerDes devices embed clock and data payloads including signal conditioning capabilities to reduce trace counts, eliminate skew issues, simplify design efforts, and provide low-cost cables/connectors for a wide variety of video, control, and imaging applications. Built-in full-speed BIST function verifies link integrity and can be used for system diagnostics.   apply Industrial imaging (machine vision) and control Security cameras and infrastructure Medical imaging