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DS92LV3221TVSX
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DS92LV3221TVSX

  • Category:Serial EEPROM
  • Product Name:20-50 MHz 32-bit channel serial link two
  • Manufacturers:NSC
  • Production Batch Number:10+
  • Encapsulation:8SOIC
  • Stock Status:There is stock
  • Stock Quantity:1000
  • Minimum order quantity: 1
  • Details:Click here to find PDF information on the DS92LV3221TVSX
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  • Product introduction

peculiarity

  • Wide operating range embedded clock for SER/DES
  • Up to 32-bit data parallel LVCMOS
  • Parallel clock from 20 to 50 MHz
  • Up to 1.6 Gbps of application data paylod
  • Simplified clock architecture
  • There is no separate serial clock line
  • There is no necessary reference clock
  • Random data receiver lock
  • On-chip signal conditioning serial connection is robust
  • Send pre-emphasis
  • Random data
  • DC balanced coding
  • The receive channel is skewed
  • Supports CAT up to 10 meters - 1.6Gbps on the 5th
  • Integrated LVDS terminal
  • Built-in AT-Speed Terminal to Terminal System Testing BIST
  • AC-coupled interconnect isolation and fault protection
  • HBM ESD protection > 4kV
  • Space-saving 64-pin TQFP package
  • Full industrial temperature range: -40 ° to +85 ° C

illustrate

The DS92LV3221 (SERVICE) serializes 32-bit data data into 2 embedded clocks for LVDS serial channels with a data payload rate that exceeds the traces of FR-4 cables such as CA, or backplane FR-4 cables to 1.6 Gbps buses. The deserialized 2 LVDS serial data channels of the DS92LV3222 (DES) de-skew the channel-to-channel delay changes and convert them into 32-bit parallel data bus LVCMOS LVDS data streams back.

On-chip data randomization/scrambling and DC-balanced coding and optional serial pre-emphasis ensure a robust, low-EMI transmission of long, lossy cables and backplanes. The deserializer autolock eliminates the need for an external reference clock synchronization mode or special incoming data, providing a simple "plug-and-lock" operation.

By embedding in the data payload, including clock signal conditioning functions, the channel second loop count SerDes device reduces tracking, eliminates offset issues, simplifies design effort, and reduces the cost of various connectors for wire/one video, control, and imaging applications. The built-in verification of link integrity in the AT high-speed BIST feature can be used to perform system diagnostics.


apply

  • Industrial imaging (machine vision) and control
  • Security cameras and infrastructure
  • Medical imaging

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Model Manufacturers lot number encapsulation illustrate
DS92LV3221TVSX NSC 10+ 8SOIC 20-50 MHz 32-bit channel serial link two

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