- Wide working range of embedded clock for SER/DES
- Up to 32-bit data parallel LVCMOS
- Parallel clocks from 20 to 50 MHz
- Up to 1.6 Gbps of application data paylod
- Simplified clock architecture
- There is no separate serial clock line
- There is no necessary reference clock
- Random data sink lock
- Robust on-chip signal regulation serial connections
- Send a pre-weight
- Random data
- DC balanced coding
- The receiving channel is skewed
- Supports CAT up to 10 meters - 1.6Gbps for 5 days
- Integrated LVDS terminal
- Built-in AT-speed end-to-end system testing BIST
- AC coupling interconnect isolation and fault protection
- > HBM ESD protection at 4kV
- Space-saving 64-pin TQFP package
- Entire industrial temperature range: -40° to +85°C
illustrate
The DS92LV3221 (service) serializes the LVDS serial channel with 2 embedded clocks with a data payload rate of 32-bit data that exceeds the traces of FR-4 cables such as the Caucasian or backplane FR-4 cable to 1.6 Gbps buses. The 2 LVDS serial data channels deserialized by the peer DS92LV3222 (DES), de-skewed the channel-to-channel delay variations, and convert them back to the LVDS data stream of the LVCMOS of the 32-bit parallel data bus.
On-chip data randomization/scrambling and DC balanced coding and optional serial pre-emphasis ensure a robust, low-EMI transmission of long, lossy cables and baseplates. The deserializer auto-lock eliminates the need for an external reference clock synchronization mode or special incoming data, providing a simple "plug-in and lock" operation.
By embedding in the data payload, including clock signal conditioning capabilities, the SerDes device reduces tracking, eliminates offset issues, simplifies design effort, and reduces the cost of a wide range of connectors for line/one-video, control, and imaging applications. The built-in verification of link integrity in AT high-speed BIST can be used to diagnose the system.
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- Industrial imaging (machine vision) and control
- Security cameras and infrastructure
- Medical imaging
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