DS99R102VS

• 3 MHz-40兆赫时钟二四1 DC-Balancing桥嵌入和数据传输
• 用户可选择时钟边缘走了并行数据两个发射机和接收机
• 编码/解码内部直流平衡——支持AC-coupling界面,没有外部编码的要求
• 个人power-down控制在两个发射机和接收机
• 嵌入式时钟CDR(时钟和数据恢复)在接收器,没有外部来源的基准时钟的需要
• 所有的这些代码RDL(随机数据锁)来支持live-pluggable应用
• 锁,以确保数据的完整性,输出国旗在接收机的一面
• 平衡T _设置 / T _持有 RCLK RDATA之间,在接收机的一面
• PTO(进步刺激)LVCMOS输出减少EMI和减少船舶保安员(SSO)的影响
• 所有的输入和LVCMOS别针内部控制下拉
• 在过滤器PLLs汉字发射机和接收机
• 48-pin TQFP包装
• 纯CMOS。 35μm过程
• 供电范围3.3 V±10%
• 0°C温度范围+ 70°C
• 8 kV恒ESD宽容

description

DS99R101/DS99R102 chipset translates 24-bit reduced parallel bus to a fully transparent data/control serial LVDS creek embedded clock information. This single serial flow transfer 24-bit reduction bus simplifies PCB wires and cables by eliminating bias issues between parallel data and clock paths. This saves system costs by reducing the PCB layer, cable width, number of connectors, and pins.

DS99R101/DS99R102 set LVDS signal in high-speed I/O. LVDS provides a low-power and low-noise environment for reliable transmission paths for serial data transmission. Operate by optimizing the serializer output edge rate and frequency range to further reduce electromagnetic interference (EMI).

Internal DC balanced encoding/decoding is used to support AC-Coupled connections.