DS99R103TVS

• 3 MHz-40兆赫时钟二四1 DC-Balancing桥嵌入和数据传输
• 能够驱动使用屏蔽双绞线
• 用户可选择时钟边缘走了并行数据两个发射机和接收机
• 编码/解码内部直流平衡——支持AC-coupling界面,没有外部编码的要求
• 个人power-down控制在两个发射机和接收机
• 嵌入式时钟CDR(时钟和数据恢复)在接收器,没有外部来源的基准时钟的需要
• 所有的这些代码RDL(随机数据锁)来支持live-pluggable应用
• 锁,以确保数据的完整性,输出国旗在接收机的一面
• 平衡T _设置 / T _持有 RCLK RDATA之间,在接收机的一面
• PTO(进步刺激)LVCMOS输出减少EMI和减少船舶保安员(SSO)的影响
• 所有的输入和LVCMOS别针内部控制下拉
• 在过滤器PLLs汉字发射机和接收机
• 100Ω输入集成终止接收机
• 4马接收器输出驱动器
• 48-pin TQFP引导和48-pin软件包
• 纯CMOS。 35μm过程
• 供电范围3.3 V±10%
• 40°C温度范围−+ 85°C
• 8 kV恒ESD宽容

description

DS99R103/DS99R104 chipset translates 24-bit parallel bus to a fully transparent data/control serial LVDS stream embedded clock information. This single serial flow transfer reduces the 24-bit bus, simplifying PCB wires and cables by eliminating deviation issues between parallel data and clock paths. This can save system costs and data paths, reducing PCB layer width, cable width, number of connectors, and pins in sequence.

DS99R103/DS99R104 sets LVDS signals at high-speed I/O. LVDS provides a low-power, low-noise environment for reliable transmission paths in serial data operations. By optimizing the serializer output edge rate, the frequency range further reduces electromagnetic interference (EMI).

In addition, the device features to enhance the signal pre-emphasis, using lossy cables further away. Internal DC balancing encoding/decoding supports AC-Coupled connections.