DS99R104TSQX

• 3 MHz - 40 MHz clock embedded and DC balanced 24:1 and 1:24 data transmission
• Capable of driving shielded twisted pair cables
• Parallel data is selected by the user for the clock edge transmitter and receiver two
• Internal DC Balanced Encoding/Decoding - Supports AC coupling without external interface coding requirements
• Personal power-down control for both transmitters and receivers
• A CDR (clock and data recovery) receiver with an embedded clock is embedded and no external reference clock source is required
• RDL (Random Data Lock) for all codes to support real-time hot-swap applications
• Lock the output flag to ensure the integrity of the data at the receiving end
• Balance t_{Set up}/ ton RCLK and RDATA_leanwith the receiver end
• The Patent and Trademark Office (gradually turned on) LVCMOS outputs to reduce EMI and minimize the impact of SSO
• All LVCMOS input and control pins have internal pull-downs
• An on-chip filter transmitter and receiver for the PLL
• Integrated 100Ω at the receiver input
• The receiver output is 4 mA driven
• 48-pin TQFP and 48-pin LLP packages
• Pure CMOS .35 micron process
• 3.3V Supply Voltage Range ± 10%
• Temperature range -40 °C to +85 °C
• ESD tolerance of 8 kV HBM

illustrate

The 24-bit parallel bus of the DS99R103/DS99R104 chipsets translates into a completely transparent data/control of the LVDS serial data stream of the embedded clock. This single serial data stream is simplified by eliminating the problem of parallel path deviations between the transmitted data and the clock compared to PCB traces and cable 24-bit buses. It saves system cost and narrows the data path, thereby reducing the number of PCB layers, cable width, and connector size and pins.

Integrated LVDS DS99R103/DS99R104 for high-speed signal I/O The low power consumption of LVDS provides reliable transmission through serial data transmission paths in a low-noise environment. Electromagnetic interference is further reduced by optimizing the edge rate of the serial output over the operating frequency range.

In addition, the device uses pre-emphasis to increase signals over longer distances using lossy cables. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects.