DS99R104TSQX

• 3 MHz-40 MHz clock embedded and DC balanced 24:1 and 1:24 data transmission
• Capable of driving shielded twisted pair cables
• The user selects both the clock edge transmitter and receiver for parallel data
• Internal DC Balanced Coding/Decoding - Supports AC coupling without external interface encoding requirements
• Personal power loss controls both transmitter and receiver
• Embedded clocks are required for CDR (clock and data recovery) receivers and no external reference clock sources
• RDL (Random Data Lock) for all code to support real-time hot-swap applications
• Lock output flags to ensure the integrity of the data at the receiving end
• Balance the RCLK and RDATA tilt on the receiving end
• The Patent and Trademark Office (gradually turned on) LVCMOS output to reduce EMI and minimize the impact of SSO
• All LVCMOS input and control pins have internal drop-downs
• The on-chip filter transmitter and receiver for the PLL
• Integrated at the receiver input termination of 100Ω
• The receiver output is driven by 4 mA
• 48-pin TQFP and 48-pin LLP packages
• Pure CMOS .35 micron process
• 3.3V supply voltage range ± 10%
• Temperature range -40°C to +85°C
• ESD tolerance of 8 kV HBM

illustrate

The converted DS99R103/DS99R104 chipset's 24-bit parallel bus becomes a fully transparent data/information that controls the LVDS serial data stream for the embedded clock. This single serial data stream simplifies the problem of deviation from the parallel paths between the transmitted data and the clock compared to the PCB traces and cables of the 24-bit bus. It saves system costs and narrows the data path, thereby reducing the number of PCB layers, cable widths, and connector sizes and pins.

The integrated LVDS DS99R103/DS99R104 I/O for high-speed signals The low power consumption of LVDS provides reliable transmission over serial data transmission paths in a low-noise environment. The output of electromagnetic interference is further reduced by the optimized edge rate serial output over the operating frequency range.

In addition, the device is pre-emphasized to increase signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-coupled interconnects.