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DS99R105VSX
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DS99R105VSX

  • Category:Serializer-deserializer
  • Product Name:3 - 40MHz DC balanced 24-bit LVDS deserializer
  • Manufacturers:NSC
  • Production Batch Number:10+
  • Encapsulation:TQFP
  • Stock Status:There is stock
  • Stock Quantity:7680
  • Minimum order quantity: 1
  • Details:Click here to find PDF information on the DS99R105VSX
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  • Product introduction

peculiarity

  • 3 MHz 40 MHz clock embedded and DC balanced 24:1 and 1:24 data transmission
  • Ability to drive shielded twisted pair cables
  • User-selectable clock edge transmitter and receive parallel data
  • Internal DC-balanced encoding/decoding - Supports an AC-coupled interface without external coding
  • Personal power-down control transmitter and reception
  • CDR (clock and data recovery) of embedded clocks is received and no external source of reference clock is required
  • All code RDL (Random Data Lock) to support field-pluggable applications
  • The LOCK output flag is flagged to ensure data integrity at the receiving end
  • Balance TSETUP/t between receiversHeldRCLK and RDATA
  • PTO (step-on) LVCMOS output to reduce EMI and minimize the effects of SSO
  • All LVCMOS input and control pins are internally pulled down
  • Filters on the transmitter and receiver PLL chips
  • In summary, the 100Ω input is terminated by the receiver
  • Output driver for a 4 mA receiver
  • 48-pin TQFP and 48-pin LLP packages
  • Pure CMOS 0.35 micron process
  • Supply voltage range: 3.3V ± 10%
  • Temperature range 0 °C to +70 °C
  • 8 kV HBM ESD tolerance

illustrate

The DS99R105/DS99R106 chipsets convert the 24-bit parallel bus into a fully transparent data/control LVDS serial data stream with embedded clock information. This single serial data stream simplifies the transmission of PCB traces and cables by eliminating skew issues between parallel data and clock paths, and transporting 24-bit buses. It saves system cost and shrinks the data path, which reduces the PCB layers, cable width, and connector size and pins.

The DS99R105/DS99R106 use LVDS high-speed I/O signals LVDS provides a low-power and low-noise environment for reliably transmitting data through the serial transmission path. By optimizing the serializer output edge rate, EMI over the operating frequency range is further reduced.

In addition, the device has a pre-emphasized signal to increase the distance to lossy cables that are no longer used. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects.

andDS99R105VSXRelated ICs are:


Model Manufacturers lot number encapsulation illustrate
NLP110-9693J artesyn 10+    
DS99R104TVS NSC 11+ TQFP-48 3 - 40MHz DC balanced 24-bit LVDS serializer
DS99R105SQ NSC 10+ LLP 3 - 40MHz DC balanced 24-bit LVDS serializer
DS99R105SQX NSC 10+ LLP 3 - 40MHz DC balanced 24-bit LVDS serializer
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DS99R106SQX NSC 10+ LLP 3 - 40MHz DC balanced 24-bit LVDS deserializer
DS99R106SQ NSC 11+ 3-40MHZDC-B 3 - 40MHz DC balanced 24-bit LVDS deserializer
DS99R106VSX NSC 09+ TQFP 3 - 40MHz DC balanced 24-bit LVDS deserializer
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