DS99R106SQX

• 3 MHz clock embedded at 40 MHz and DC-balanced 24:1 and 1:24 data transmission
• Capable of driving shielded twisted pair cables
• User-selectable clock edge transmitter and receive parallel data
• Internal DC Balanced Coding/Decoding - Supports AC coupled interfaces without external coding
• Personal power-down controls transmitter and reception
• CDR (Clock and Data Recovery) for embedded clocks receives and does not require an external source for reference clocks
• All code RDL (Random Data Lock) to support field pluggable applications
• LOCK output flag to ensure data integrity, on the receiving end
• Balance RCLK and RDATA held between T SETUP/T recipients
• PTO (step-by-step) LVCMOS output to reduce EMI and minimize the impact of SSO
• All LVCMOS inputs and control pins are pulled down inside
• Filters on the transmitter and receiver phase-locked loop chips
• In summary, the 100Ω input termination receiver
• 4 mA receiver output driver
• 48-pin TQFP and 48-pin LLP packages
• Pure CMOS 0.35 micron process
• Supply voltage range: 3.3V ± 10%
• Temperature range 0°C to +70°C
• 8,000 volts HBM ESD tolerance

illustrate

DS99R105/DS99R106 chipset converts into a fully transparent 24-bit parallel bus for LVDS serial data streams with fully transparent data/control with embedded clock information. This single serial data stream simplifies the transmission of PCB traces and cables over the 24-bit bus by eliminating the problem of bias between parallel data and clock paths. It saves system costs and narrows the data path, which reduces the size and pins of PCB layers, cable widths, and connectors.

DS99R105/DS99R106 adopts LVDS high-speed I/O signal LVDS provides a low-power and low-noise environment for reliably transmitting data over a serial transmission path. By optimizing the serializer output edge rate, the operating frequency range EMI is further reduced.

In addition, the device has a pre-emphasis on signals that increase the distance to where the lossy cable is no longer in use. Internal DC balanced encoding/decoding is used to support AC-coupled interconnects.