DS99R421QSQ

• 5 MHz, 43 MHz embedded clock and DC-balanced data transmission (21 LVDS data bits plus 3 low-speed LVCMOS data bits)
• User-adjustable pre-weighted driving capability via external resistor LVDS output and capability to drive up to 10 meters shielded twisted pair cable
• Supports AC coupled data transmission
• LVDS input integrated terminal resistor 100Ω
• Power loss control
• @speed BIST self-DS90UR124 can be used to verify link integrity
• All LVCMOS inputs and control pins pull down inside
• OS [2:0] Schmidt triggers the input to minimize metastable conditions.
• The output tristate is through dengue
• Phase-locked loop chip filter
• Supply voltage range: 3.3V ± 10%
• The temperature range of the car is from -40 ° C to +105 ° C
• ESD tolerance greater than 8kV
• Compliant with ISO 10605 ESD and AEC - Q100 standards

illustrate

DS99R421 convert one FPD-Link input with 4 non-DC balanced LVDS (3 LVDS data + LVDS clock) plus 3 oversampled to a single LVDS DC-balanced low-speed control bit for serial data stream with embedded clock information. This simplified transmission of a single serial data stream exceeds the deviation problem between 3 parallel LVDS data inputs and LVDS clock paths, eliminating the 24-bit bus for a single differential PCB trace and cable. It saves system costs, shrinking 4 LVDS pairs and 1 LVDS pair, thereby reducing the size of PCB layers, width cables, connectors, and pins.

DS99R421 uses a single serialized I/O high-speed LVDS signal The reliable transmission of data over the LVDS serial transmission path of the embedded clock provides a low-power and low-noise environment. EMI is further reduced by optimizing the edge rate range of the output of the operating frequency converter.

In addition, the device has a pre-emphasis on signals that increase the distance to where the lossy cable is no longer in use. Internal DC balanced coding is used to support AC-coupled interconnects.