DS99R421QSQX

• 5 MHz, 43 MHz embedded clock and DC-balanced data transmission (total 21 LVDS data bits plus 3 low-speed LVCMOS data bits)
• User-adjustable pre-emphasis driving capability via external resistor LVDS output and capability to drive up to 10 meters of shielded twisted pair cable
• Supports AC-coupled data transmission
• The LVDS input has an integrated termination resistor of 100Ω
• Power-down control
• The @speed BIST self-DS90UR124 can be used to verify link integrity
• All LVCMOS inputs and control pins are internally pulled down
• OS [2:0] Schmidt triggers inputs to minimize metastable conditions.
• Output tri-state through dengue
• PLL chip filter
• Supply voltage range: 3.3V ± 10%
• The automotive temperature range is -40 °C to +105 °C
• ESD tolerance greater than 8kV
• Complies with ISO 10605 ESD and AEC - Q100 standards

illustrate

The DS99R421 converts one FPD-Link input with four non-DC-balanced LVDS (3 LVDS data + LVDS clock) plus 3 oversamples into a single LVDS-DC balanced control bit for a serial data stream with embedded clock information. This simplified transmission of a single serial data stream eliminates the problem of skew between more than 3 parallel LVDS data inputs and the LVDS clock path, eliminating the 24-bit bus to a single differential PCB trace and cable. It saves system cost by shrinking 4 LVDS pairs and 1 LVDS pair, thereby reducing PCB layers, cable width, connector size, and pins.

The DS99R421 uses a single serialized I/O high-speed LVDS signal The reliable transmission of data over the LVDS serial transmission path of the embedded clock provides a low-power and low-noise environment. EMI is further reduced by optimizing the edge rate range of the operating frequency converter output.

In addition, the device has a pre-emphasized signal to increase the distance to lossy cables that are no longer used. Internal DC balancing coding is used to support AC-coupled interconnects.