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H5TQ2G83CFR-H9C
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H5TQ2G83CFR-H9C

  • Category:Battery management
  • Product Name:Power chip
  • Manufacturers:Hynix
  • Production Batch Number:10+
  • Encapsulation:FBGA
  • Stock Status:There is stock
  • Stock Quantity:2880
  • Minimum order quantity: 1
  • Details:Click here to find pdf information on H5TQ2G83CFR-H9C
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  • Product introduction

Featurespeculiarity

  • VDD=VDDQ=1.5V +/- 0.075VVDD = VDDQ = 1.5V + / - 0.075V
  • Fully differential clock inputs (CK, /CK) operationFully differential clock input (CK/CK) operation
  • Differential Data Strobe (DQS, /DQS)Differential Data Gating (DQS/DQS)
  • On chip DLL align DQ, DQS and /DQS transition with CKtransitionIn conjunction with the chip's DLL CKtransition DQ, DQS and /DQS transitions
  • DM masks write data-in at the both rising and fallingedges of the data strobeMark mask write data are rising, data gating fallingedges
  • All addresses and control inputs except data,data strobes and data masks latched on therising edges of the clockAll addresses and controls input data, data gating and data masks except the latching edge of the clock
  • Programmable CAS latency 5, 6, 7, 8, 9, 10 and (11)supportedSupports programmable CAS delay 5, 6, 7, 8, 9, 10(11)
  • Programmable additive latency 0, CL-1, and CL-2supportedProgrammable additional delays 0, CL-1 and CL-2supported
  • Programmable CAS Write latency (CWL) = 5, 6, 7, 8Programmable CAS Write Delay (CWL) = 5,6,7,8
  • Programmable burst length 4/8 with both nibblesequential and interleave modeNibblesequential and interleaved modes are programmable with a burst length of 4/8
  • BL switch on the flyFly on the "Basic Law" switch
  • 8banks8banks
  • Average Refresh Cycle(Tcase of 0 °C~ 95 °C)Average update cycle (TCASE 0°C to 95°C)
    - 7.8 µs at 0°C ~ 85 °C- 7.8 microseconds for 0°C to 85°C
    - 3.9 µs at 85°C ~ 95 °C- 3.9 μs at 85 ° C to 95 ° C
  • Auto Self Refresh supportedAutomatic self-refresh support
  • JEDEC standard 82ball FBGA(x4/x8), 96ball FBGA (x16)JEDEC standard 82ball FBGA (x4/x8), 96ball with FBGA (X16)
  • Driver strength selected by EMRSEMRS selected drive strength
  • Dynamic On Die Termination supportedDynamic mode support is terminated
  • Asynchronous RESET pin supportedSupports asynchronous reset pins
  • ZQ calibration supportedSupport ZQ calibration
  • TDQS (Termination Data Strobe) supported (x8 only)TDQS (End of Data Gating) support (X8 only)
  • Write Levelization supportedWrite levelization support
  • 8 bit pre-fetch8-bit prefetch
  • This product in compliance with the RoHS directiveThis is a RoHS compliant product

 

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