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VDD=VDDQ=1.5V +/- 0.075V VDD = VDDQ = 1.5V + / - 0.075V
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Fully differential clock inputs (CK, /CK) operation
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Differential Data Strobe (DQS, /DQS)
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On chip DLL align DQ, DQS and /DQS transition with CKtransition in the DLL with chip CKtransition DQ, DQS and/DQS transition
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DM masks write data-in at the both rising and fallingedges of the data strobe
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All addresses and control inputs except data,data strobes and data masks latched on therising edges of the clock
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Programmable CAS latency 5, 6, 7, 8, 9, 10 and (11)
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Programmable additive latency 0, CL-1, and CL-2supported
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Programmable CAS Write latency (CWL) = 5, 6, 7, 8 Programmable CAS Write Latency (CWL) = 5, 6, 7, 8
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Programmable burst length 4/8 with both nibblesequential and interleave mode nibblesequential and interleave mode programmable burst length of 4/8
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BL switch on the fly
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8banks 8banks
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Average Refresh Cycle (Tcase of 0 °C ~ 95 °C)
- 7.8 μs at 0°C ~ 85 °C - 7.8 μs for 0°C to 85°C
- 3.9 μs at 85°C ~ 95°C - 3.9 μs at 85°C to 95°C
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Auto Self Refresh supported
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JEDEC standard 82ball FBGA(x4/x8), 96ball FBGA (x16) JEDEC standard 82ball FBGA(x4/x8), 96ball FBGA(x16)
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Driver strength selected by EMRS EMRS选定的驱动强度
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Dynamic On Die Termination supported
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Asynchronous RESET pin supported
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ZQ calibration supported
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TDQS (Termination Data Strobe) supported (x8 only) TDQS（终止数据选通）支持（X8只）
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Write Levelization supported
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8-bit pre-fetch 8-bit prefetch
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This product in compliance with the RoHS directive