HMC855LC5 is a 1:4 deplexer designed for up to 28 Gbps data deserialization applications. The device uses the rising and falling edges of a half-rate clock to sample the input data sequence D0-D3 and latch the data to the differential output. A 1/4 rate clock output signal is generated on-chip that can be used to read data to other devices. The demultiplexer is DC-coupled and supports broadband operation.
All clock and data inputs of the HMC855LC5 are CML and terminated to the positive supply GND via an on-chip 50 Ω, which can be DC or AC coupled. The differential output source is terminated to 50 Ω and can also be AC or DC coupled. The outputs can be connected directly to a 50-Ω ground termination system or to input driver devices via CML logic. HMC855LC5 also integrates an output level control pin VR for loss compensation or signal level optimization. HMC855LC5 operates from a single -3.3V supply and is available in a RoHS-compliant 5x5 mm SMT package.
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SONET OC-192
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宽带测试和测量
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串行数据传输高达28 Gbps
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FPGA接口