HMC954LC4B is a 2:1 multiplexer designed for 32 Gbps data serial applications. The multiplexer latches two differential inputs at the rising edge of the input clock. The device uses the rising and falling edges of a half-rate clock to transmit data serially. HMC954LC4B also integrates an output level control pin VR that can be used for loss compensation or signal level optimization.
All differential inputs HMC954LC4B are CML and terminated to the positive supply GND via an on-chip 50 Ω, and can be AC or DC coupled. The differential CML output source is terminated to 50 Ω and can also be AC or DC coupled. The outputs can be connected directly to a 50-Ω ground termination system or to input driver devices via CML logic. HMC954LC4B operates from a single -3.3 V supply and is available in a RoHS-compliant 4x4 mm SMT ceramic package.
apply
-
SONET OC-192
-
宽带测试和测量设备
-
FPGA接口电路
-
16 G和32 G光纤通道
-
100 Gb以太网