ISL23425

• Product Introduction

Key features:

Each pack contains two potentiometers 256-resistor faucets It is a total resistance of 10kΩ, 50kΩ, or 100kΩ SPI serial interface No extra level is converted to low bus power supply Multiple taxable licenses for daisy-linked chains Maximum supply current without serial bus activity (standby) 4μ A@ V CC and V logic = 5V 1.7μ A@ V CC and V logic = 1.7V Shutdown mode By the end of the year, the troops entered the terminal with open circuits and internal connections to RLI via RWI DCP The DCP resistor is disconnected from the circuit to reduce power consumption Power supply V CC = 1.7V to 5.5V analog power supply Up to five logic = SPI bus/logic power supply from 1.2V to 5.5V Tap resistance: 70Ω Typical@ V, CC = 3.3V Power-on preset to medium scale (128 tap) Expanded industrial temperature range: -40°C to +125°C 14 LD TSSOP or 16 LDμTQFN packs Lead-free (RoHS compliant) Description

ISL23425 is a volatile, low-voltage, low-noise, low-power, 256-tap, dual-numerical potentiometer (DCP) SPI bus ™ interface. It integrates two DCP cores: the wiper switch and control logic in a monolithic CMOS integrated circuit. Each digital control potentiometer is achieved by combining resistive elements and CMOS switches. The position of the wipers is controlled by the user via the SPI bus interface. Each potentiometer has a related volatile wiper registration (WRI, I = 0,1), which can be directly written and read to the user. WRI content controls the position of the wipers. At startup, each DCP's wipers always start at a medium scale (128-tap position), low voltage, low power consumption, and small package ISL23425, making them an ideal choice for battery-powered devices. Additionally, the ISL23425 has a V-logic pin that allows the bus to operate at 1.2V, with a V-independent CC value. This allows DCPs to be used in various applications, including as a three-terminal potentiometer or a two-terminal variable resistor control, with parameters not connected directly via voltage level converters, ISL23425 low logic levels. Adjustment and signal processing.