LM3S1968-IQC50-A2

• Product Introduction

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overview

　　Texas Instruments' range of microcontrollers from Stellaris® is the first ARM® CortexTM-M3-based controller that brings high-performance 32-bit computing power to particularly cost-sensitive embedded microcontroller applications. These technology-leading chips enable users to enjoy 32-bit performance at the price point of traditional 8-bit and 16-bit devices, and all models are available in a small footprint package.  　　The Stellaris® family of chips delivers efficient performance and a wide range of integration capabilities to better enable devices in cost-critical applications that require efficient control over processing and connectivity. LM3S1968 microcontrollers have battery-backup hibernation modules that effectively power down LM3S1968 and put the device into a low-power state during long periods of downtime, making it ideal for applications that require minimal power consumption.  　　The advantage of LM3S1968 microcontrollers is also the easy use of a variety of ARM development tools and underlying IP solutions for system-on-chips (SoCs), as well as a wide user base. In addition, the microcontroller uses the ARM Thumb-compatible® Thumb2 instruction set to reduce the need for storage capacity and thereby reduce costs. Finally, LM3S1968 microcontrollers are code-compatible with all members of the Stellaris® family, which provides users with the flexibility to adapt to a variety of precise needs. 　　To help users get to market quickly, Texas Instruments offers a comprehensive suite of solutions, including evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a robust support, sales, and distributor network. Features LM3S1968 The microcontroller includes the following features: 32-bit RISC performance 　　　            -Uses 32-bit ARM®CortexTM-M3 v7M architecture optimized for small package applications 　　　            -System timer (SysTick) is available, including a simple 24-bit write-zero, decrementing, self-loading counter with flexible control mechanisms 　　　            - Only Thumb-2 instruction set compatible with Thumb® is used for higher code density 　　　            •Operating frequency is 50-MHz 　　　            - Hardware division and single-cycle multiplication 　　　            •Integrated Nested Vector Interrupt Controller (NVIC) for easier handling of interrupts 　　　            - 40 interrupts with 8 priorities 　　　            - The Memory Protection Unit (MPU) provides a privileged mode to protect the functionality of the operating system 　　　            - Non-aligned data access to enable more efficient placement of data into memory 　　　            -Precise bit-banding not only maximizes memory space but also improves peripheral control Internal memory 　　　            -256 KB single-cycle Flash 　　　　User-managed Flash blocks are protected in 2KB blocks 　　　　Flash data programmable by user management 　　　　Flash protection blocks that can be defined and managed by the user 　　　            -64 KB single-cycle SRAM Universal timer 　　　            •4 Universal Timer Modules (GPTM), each capable of providing 2 16-bit timers/counters Each universal timer module can be configured as a standalone timer or event counter, used as a single 32-bit timer or as a 32-bit real-time clock (RTC) to capture events, or as a pulse-width modulation output (PWM), or to trigger analog-to-digital conversion 　　　            •32-bit timer mode 　　　　Programmable single-trigger timer 　　　　Programmable cycle timer 　　　　It can be used as a real-time clock when connected to a 32.768KHz external clock input 　　　　When the controller enables the CPU pause flag during debugging, the user can enable stalling in both periodic and single-trigger modes 　　　　ADC event triggered 　　　            •16-bit timer mode 　　　　Universal timer function with an 8-bit pre-divider 　　　　Programmable single-trigger timer 　　　　Programmable cycle timer 　　　　When the controller enables the CPU pause flag during debugging, the user can enable stalling 　　　　ADC event triggered 　　　            - 16-bit input capture mode 　　　　Provides input edge count capture 　　　　Provides input edge time capture function 　　　            - 16-bit PWM mode 　　　　Simple PWM mode, the reversal of PWM signal output can be determined by software programming Watchdog timer that follows the ARM FiRM specification 　　　            •32-bit minus counter with programmable loading registers 　　　            •Independent watchdog clock with enable function 　　　            •Programmable interrupt occurrence logic with interrupt shielding 　　　            -Lock register protection is provided to prevent software from runaway 　　　            - Reset occurrence logic with enable/disabled energy 　　　            - User can enable stalling when the controller enables the CPU pause flag to be active during debugging Synchronous Serial Interface (SSI) 　　　            -2 SSI modules, each with the following characteristics: 　　　            - Host or slave operation 　　　            •Programmable control of clock bit rate and pre-division 　　　            •Independent transmit and receive FIFO, 16 bits wide, 8 bits deep 　　　            •Programmable interface for connection to Freescale's SPI interface, synchronous serial interface for MICROWIRE or TI (Texas Instruments) devices 　　　            •Programmable data frame size ranging from 4 to 16 bits 　　　            •Internal cycle test mode can be used for diagnostic/debugging tests UART 　　　            •3 fully programmable 16C550-type UARTs with IrDA support 　　　            - Independent 16×8 transmit (TX) and 16×12 receive (RX) FIFOs to reduce CPU interruption service load (loading) 　　　            •Programmable baud rate generator with decimal crossover 　　　            •Programmable to set FIFO length, including 1-byte depth operation to provide a traditional dual-buffer interface 　　　            -FIFO trigger levels can be set to 1/8, 1/4, 1/2, 3/4 and 7/8 　　　            -Standard asynchronous communication bits: start bit, stop bit, odd-even bit 　　　            •Invalid start position detection 　　　            - Occurrence and detection of line interruptions ADC 　　　            •Single input and differential input configurations 　　　            •8 10-bit channels (inputs) used as single-terminal inputs 　　　            •Sampling rate: 1,000,000 samples/sec 　　　            •Flexible, configurable analog-to-digital conversion 　　　            •4 programmable sample conversion sequences from 1 to 8 units (entries) long with corresponding conversion result FIFO 　　　            •Each sequence is triggered by software or internal events (timer, analog comparator, PWM or GPIO). 　　　            •On-chip temperature sensor Analog comparator 　　　            •3 independently integrated analogue comparators 　　　            -The outputs can be configured to drive the output pin, generate an interrupt, or an ADC sampling sequence 　　　            •Compare two external pin inputs or compare an external pin input to an internal programmable reference voltage I2C 　　　            •2 I2C modules 　　　            •Speeds of host and slave receive and transmit operations up to 100Kbps in standard mode and up to 400Kbps in fast mode 　　　            - Generation of interruptions 　　　            - The host comes with quorum and clock synchronization, supports multiple hosts, and 7-bit addressing mode PWM 　　　            •3 PWM generator modules, each with 1 16-bit counter, 2 comparators, 1 PWM signal generator, and a dead-band generator 　　　            - 1 x 16-digit counter 　　　　Runs in decremental or incremental/decremental mode 　　　　The output frequency is controlled by a 16-bit loading value 　　　　Synchronously update the payload values 　　　　An output signal is generated when the counter value reaches zero or the loading value 　　　            - 2 x PWM comparators 　　　　Updates to comparator values can be synchronized 　　　　Output signal is generated when matching 　　　            •PWM signal generator 　　　　The PWM output signal is generated based on the output signal of the counter and PWM comparator 　　　　Two independent PWM signals can be generated 　　　            •Dead zone generator 　　　　Generates 2 PWM signals with programmable dead delay for driving half-H bridges 　　　　Can be bypassed without modifying the input PWM signal 　　　            •Flexible output control module with PWM output enable for each PWM signal 　　　　Each PWM signal has a PWM output enable 　　　　Each PWM signal can be optionally inverted (polarity controlled) 　　　　Each PWM signal can be optionally fault-handled 　　　　Timer synchronization of PWM generator modules 　　　　The PWM generator module's timer/comparator update synchronization 　　　　PWM generator module interrupt status summary 　　　            •ADC sampling sequence can be initiated QEI 　　　            •2 QEI modules 　　　            •Hardware position integrator tracks encoder position 　　　            - Speed capture uses a built-in timer 　　　            -Interrupts occur when index pulses, speed timer time arrives, direction changes, or orthogonal error detection GPIO 　　　            •Up to 5-52 GPIOs, depending on configuration 　　　            •Input/output can withstand 5V 　　　            •Interrupt generation can be programmed to edge trigger or level detection 　　　            - Bit shielding by address lines in read and write operations 　　　            •ADC sampling sequence can be initiated 　　　            •Programmable control of GPIO port configuration 　　　　Weak pull-up or pull-down resistance 　　　　2mA, 4mA, and 8mA port drivers 　　　　8-mA-driven slope control 　　　　Open and leak enabled 　　　　Digital input enablement power supply 　　　            •On-chip dropout (LDO) regulator with programmable output voltage and user-adjustable range of 2.25V to 2.75V 　　　            •Hibernation mode handles power-up/power-down 3.3V sequences and controls kernel digital logic and analog circuitry 　　　            - Low power options for controllers: sleep mode and deep sleep mode 　　　            - Low-power selection of peripherals: Software controls the shutdown of individual peripherals 　　　            •LDO with detection of non-adjustable voltage and automatic reset, which can be controlled and enabled by the user 　　　            -3.3V power loss detection, which can be reported by interrupt or reset Flexible reset source 　　　            •Power-On Reset (POR) 　　　            •Reset pins are effective 　　　            •Power-down (BOR) detector alerts the system to a power drop 　　　            - Software reset 　　　            - Watch dog timer reset 　　　            •Internal low-dropout (LDO) regulator output becomes unstable Other characteristics 　　　            -6 reset sources 　　　            •Programmable clock source control 　　　            -Strobe the clock of individual peripherals to save power consumption 　　　            - Test Access Port (TAP) controller that follows IEEE 1149.1-1990 standards 　　　            - Debug access via JTAG and serial line interfaces 　　　            - Full JTAG boundary scanning Industry-wide RoHS compliant 100-pin LQFP package

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