- 100% software compatible CLC5903
- In addition to analog input and reference part pin-compatible CLC5903
- CLC5526 DVGA (200 dB dynamic range at 123 kHz)
- Precision benchmarks on chips
- User-programmable AGC with enhanced power detector
- The channel filter includes a 21-tap, 63-tap symmetrical FIR fourth-order CIC secondary
- Flexible output formats
- Serial and parallel output ports
- JTAG boundary scan
- 8-bit microprocessor interface
- 128-pin PQFP
illustrate
The LM97593 Dual-Channel ADC/Digital Tuner/Automatic Gain Control IC for Dual-Channel Digital Downconverter (DDC) with integrated 12-bit analog-to-digital converter (ADC) and Automatic Gain Control (AGC). LM97593 further enhance the country's receiver integration chipset (DRCS) with DDC wide-bandwidth dual-channel ADC cores. Includes one of the complete NDRCs LM97593 dual-channel ADCs/digital tuners/AGCs and two CLC5526 digitally controlled variable gain amplifiers (DVGAs). The system can directly sample the signal in the mid-frequency, enhancing the performance of the receiver and reducing the system cost by 300MHz. One is DRCS based on narrowband communication system block diagram 。
LM97593 based on digital signal processing (DSP) technology that provides digital tuning and filtered hardwired with high dynamic range. Each channel has independent adjustments, phase offset, factor of filters, and gain settings. Channel filtering consists of a series of triple filters. The first is a 4-step cascade integral comb (CIC) filter with programmable extraction ratios from 8 to 2048. This is followed by two symmetrical FIR filters, 21 taps, 63 taps, two independent programmable factors. The data in the first FIR filter extraction 2 is determined by the FIR by 2 or 4 seconds. The channel filter bandwidth 52MSPS ranges from ± up and down to 650kHz ± 1.3kHz. At 65MSPS, the maximum bandwidth increase is ± 812kHz.
The LM97593 AGC controls the display's ADC output and the ADC's input signal level control by adjusting the DVGA settings. AGC threshold, dead zone + hysteresis, and loop time constants are user-defined. The total dynamic range of 123 dB greater than the full scale signal is 200kHz, and the bandwidth noise can reach the diversity of the receiving chip.
Key specifications:
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Internal ADC resolution
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12th place
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Sampling rate
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65 MSPS |
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Signal-to-noise ratio (= 11-bit F at 250MHz, Nyquist)
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62 dBFS (typical)
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SNR (f at = 250MHz, 200kHz)
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83 dBFS (typical)
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SFDR (F, = 11-bit Nyquist at 250MHz)
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68 dBFS (typical)
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Full power bandwidth
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650 MHz (typical)
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Power Consumption (65MSPS)
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560 mW (typical)
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apply
- Cellular base stations
- GSM/GPRS/EDGE/GSM Stage 2 receiver
- Satellite receiver
- Wireless local loop receiver
- Digital
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